NXP Semiconductors MC9S12VRP64, Owner Reference Manual

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Device Overview S12VRP-Series
MC9S12VRP Family Reference Manual Rev. 1.3
NXP Semiconductors 27
Reserved register space shown in Table 1-3 is not allocated to any module.
This register space is reserved for future use. Writing to these locations has
no effect. Read access to these locations returns zero.
Figure 1-2 shows S12VRP-Series CPU and BDM local address translation to the global memory map as
a graphical representation. The whole 256K global memory space is visible through the P-Flash window
located in the 64k local memory map located at 0x8000 - 0xBFFF using the PPAGE register.
NOTE
Flash space on page 0xC in Figure 1-2 is not available on S12VRP48.
0x0280–0x02EF Reserved 112
0x02F0–0x02FF CPMU (clock and power management) 16
0x0300–0x03FF Reserved 256
Table 1-4. S12VRP-Series Memory Address Ranges
Device Memory Size Address
S12VRP48
4 KB Data-Flash
SRAM 6 KB 0x2800-0x3FFF
Data Flash 2 KB 0x0400-0x0BFF
Program Flash 48 KB Page D, E and F
S12VRP64
SRAM 6 KB 0x2800-0x3FFF
Data Flash 4 KB 0x0400-0x13FF
Program Flash 64KB Page C, D, E and F
Address Module
Size
(Bytes)