NXP Semiconductors MC9S12VRP64, Owner Reference Manual

Page: 345 / 555

Timer Module (TIM16B2CV3)
MC9S12VRP Family Reference Manual Rev. 1.3
NXP Semiconductors 345
11.3.2.2 Timer Compare Force Register (CFORC)
Read: Anytime but will always return 0x0000 (1 state is transient)
Write: Anytime
11.3.2.3 Timer Count Register (TCNT)
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
Read: Anytime
Write: Has no meaning or effect in the normal mode; only writable in special modes .
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED FOC1 FOC0
Reset 0 0 0 0 0 0 0 0
Figure 11-5. Timer Compare Force Register (CFORC)
Table 11-3. CFORC Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field Description
1:0
FOC[1:0]
Note: Force Output Compare Action for Channel 1 :0 — A write to this register with the corresponding data
bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action
taken is the same as if a successful comparison had just taken place with the TCx register except the
interrupt flag does not get set. If forced output compare on any channel occurs at the same time as the
successful output compare then forced output compare action will take precedence and interrupt flag won’t
get set.
15 14 13 12 11 10 9 9
R
TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8
W
Reset 0 0 0 0 0 0 0 0
Figure 11-6. Timer Count Register High (TCNTH)
7 6 5 4 3 2 1 0
R
TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0
W
Reset 0 0 0 0 0 0 0 0
Figure 11-7. Timer Count Register Low (TCNTL)