NXP Semiconductors MC9S12VRP64, Owner Reference Manual

Page: 86 / 555

Port Integration Module (S12VRPPIMV1)
MC9S12VRP Family Reference Manual Rev. 1.3
86 NXP Semiconductors
2.4.7.1 XIRQ, IRQ Interrupts
The XIRQ pin allows requesting non-maskable interrupts after reset initialization. During reset, the X bit
in the condition code register is set and any interrupts are masked until software enables them.
The IRQ pin allows requesting asynchronous interrupts. The interrupt input is disabled out of reset. To
enable the interrupt the IRQCR[IRQEN] bit must be set and the I bit cleared in the condition code register.
The interrupt can be configured for level-sensitive or falling-edge-sensitive triggering. If IRQCR[IRQEN]
is cleared while an interrupt is pending, the request will de-assert.
Both interrupts are able to wake-up the device from stop mode. Means for glitch filtering are not provided
on these pins.
2.4.7.2 Pin Interrupts and Key-Wakeup (KWU)
Ports AD, P and L offer pin interrupt and key-wakeup capability. The related interrupt enable (PIE) as well
as the sensitivity to rising or falling edges (PPS) can be individually configured on a per-pin basis. All
bits/pins in a port share the same interrupt vector. Interrupts can be used with the pins configured as inputs
or outputs.
An interrupt is generated when a bit in the port interrupt flag (PIF) and its corresponding port interrupt
enable (PIE) are both set. The pin interrupt feature is also capable of waking up the CPU when it is in stop
or wait mode (key-wakeup).
A digital filter on each pin prevents short pulses from generating an interrupt. A valid edge on an input is
detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active
level. Else the sampling logic is restarted.
In run and wait mode the filters are continuously clocked by the bus clock. Pulses with a duration of
t
PULSE
< n
P_MASK
/f
bus
are assuredly filtered out while pulses with a duration of t
PULSE
> n
P_PASS
/f
bus
guarantee a pin interrupt.
In stop mode the filter clock is generated by an RC-oscillator. The minimum pulse length varies over
process conditions, temperature and voltage. Pulses with a duration of t
PULSE
< t
P_MASK
are assuredly
filtered out while pulses with a duration of t
PULSE
> t
P_PASS
guarantee a wakeup event ( Figure 2-34 ).
Please refer to the “Pin Interrupt Characteristics” in the device electrical specification for pulse length
limits.
To reduce current consumption the RC oscillator is active only for a short phase following a detected edge
on any pin whose interrupt flag is not set (PIF[x]=0).
Port AD pin interrupt PIE1AD[PIE1AD]
Port P pin interrupt PIEP[PIEP]
Port L pin interrupt PIEL[PIEL]
Port P over-current interrupt OCIEP[OCIEP]
Table 2-41. PIM Interrupt Sources
Module Interrupt Sources Local Enable