NXP Semiconductors MC9S12VRP64, Owner Reference Manual

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Device Overview S12VRP-Series
MC9S12VRP Family Reference Manual Rev. 1.3
32 NXP Semiconductors
1.8.2.17.3 LPRXD Signal
This signal is the LINPHY receive output.
1.8.2.18 SCI Signals
1.8.2.18.1 RXD[1:0] Signals
These signals are associated with the receive functionality of the serial communication interfaces SCI1-0.
1.8.2.18.2 TXD[1:0] Signals
These signals are associated with the transmit functionality of the serial communication interfaces SCI1-0.
1.8.2.19 PWM[7:0] Signals
The signals PWM[7:0] are associated with the PWM module outputs.
1.8.2.20 Internal Clock outputs
1.8.2.20.1 ECLK
This signal is associated with the output of the divided bus clock (ECLK).
NOTE
This feature is only intended for debug purposes at room temperature.
It must not be used for clocking external devices in an application.
1.8.2.21 ETRIG[1:0]
These signals are inputs to the Analog-to-Digital Converter. Their purpose is to trigger ADC conversions.
1.8.2.22 IOC0_[1:0] Signals
The signals IOC0_[1:0] are associated with the input capture or output compare functionality of the timer
(TIM0) module.
1.8.2.23 IOC1_[1:0] Signals
The signals IOC1_[1:0] are associated with the input capture or output compare functionality of the timer
(TIM1) module.
1.8.3 Power Supply Pins
S12VRP-Series power and ground pins are described below. Because fast signal transitions place high,
short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible.