NXP Semiconductors MC9S12VRP64, Owner Reference Manual

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64 KByte Flash Module (S12FTMRG64K4KV2)
MC9S12VRP Family Reference Manual Rev. 1.3
438 NXP Semiconductors
18.1 Introduction
The FTMRG64K4K module implements the following:
• 64Kbytes of P-Flash (Program Flash) memory
• 4Kbytes of D-Flash memory
The Flash memory is ideal for single-supply applications allowing for field reprogramming without
requiring external high voltage sources for program or erase operations. The Flash module includes a
memory controller that executes commands to modify Flash memory contents. The user interface to the
memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is
written to with the command, global address, data, and any required command parameters. The memory
controller must complete the execution of a command before the FCCOB register can be written to with a
new command.
CAUTION
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes
and aligned words. For misaligned words access, the CPU has to perform twice the byte read access
command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0.
It is possible to read from P-Flash memory while some commands are executing on D-Flash memory. It
is not possible to read from D-Flash memory while a command is executing on P-Flash memory.
Simultaneous P-Flash and D-Flash operations are discussed in
Section 18.4.5 .
Both P-Flash and D-Flash memories are implemented with Error Correction Codes (ECC) that can resolve
single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that
programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read
by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word
accessed will be corrected.
18.1.1 Glossary
Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including
program and erase) on the Flash memory.
D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store for data.
D-Flash Sector — The D-Flash sector is the smallest portion of the D-Flash memory that can be erased.
The D-Flash sector consists of 256 bytes.
NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters
required for Flash command execution.
Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two
sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double
bit fault detection within each double word.