NXP Semiconductors MC9S12VRP64, Owner Reference Manual

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S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V8)
MC9S12VRP Family Reference Manual Rev. 1.3
162 NXP Semiconductors
The internal reset of the MCU remains asserted while the reset generator completes the 768 PLLCLK
cycles long reset sequence. In case the RESET pin is externally driven low for more than these 768
PLLCLK cycles (External Reset), the internal reset remains asserted longer.
Figure 4-38. RESET Timing
4.5.3 Oscillator Clock Monitor Reset
If the external oscillator is enabled (OSCE=1) and the oscillator clock monitor reset is enabled (OMRE=1),
then in case of loss of oscillation or the oscillator frequency drops below the failure assert frequency f
CMFA
(see device electrical characteristics for values), the S12CPMU_UHV_V8 generates an Oscillator Clock
Monitor Reset. In Full Stop Mode the external oscillator and the oscillator clock monitor are disabled.
4.5.4 PLL Clock Monitor Reset
In case of loss of PLL clock oscillation or the PLL clock frequency is below the failure assert frequency
f
PMFA
(see device electrical characteristics for values), the S12CPMU_UHV_V8 generates a PLL Clock
Monitor Reset. In Full Stop Mode the PLL and the PLL clock monitor are disabled.
4.5.4.1 Computer Operating Properly Watchdog (COP) Reset
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. When the COP is being used, software is responsible for keeping the COP from
timing out. If the COP times out it is an indication that the software is no longer being executed in the
intended sequence; thus COP reset is generated.
The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL0 and COPOSCSEL1 bit.
)
(
)
PLLCLK
512 cycles
256 cycles
S12_CPMU drives
possibly
RESET
driven
low
)
(
(
RESET
S12_CPMU releases
f
VCORST
RESET pin low
RESET pin
f
VCORST