NXP Semiconductors MC9S12VRP64, Owner Reference Manual

Page: 155 / 555

S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V8)
MC9S12VRP Family Reference Manual Rev. 1.3
NXP Semiconductors 155
4.4.2 Startup from Reset
An example for startup of the clock system from Reset is given in Figure 4-34 .
Figure 4-34. Startup of clock system after Reset
System
PLLCLK =
Reset
f
VCORST
CPU
reset state
vector fetch, program execution
LOCK
POSTDIV
$03 (default target f
PLL
=f
VCO
/4 = 12.5MHz)
f
PLL
increasing
f
PLL
=12.5MHz
t
lock
SYNDIV
$18 (default target f
VCO
=50MHz)
$00
f
PLL
=50MHz
example change
of POSTDIV
) (
RESET
Pin
) (
768 cycles
startup
f
VCORST
n
STARTUP
cycles
f
BUS
512 cycles
f
VCORST
256 cycles
f
VCORST
Core Clock
Bus Clock =
f
BUS
increasing
f
BUS
=6.25MHz
f
BUS
=25MHz
) ( ) (
Core Clock/2