NXP Semiconductors MC9S12VRP64, Owner Reference Manual

Page: 283 / 555

Pulse-Width Modulator (S12PWM8B8CV2)
MC9S12VRP Family Reference Manual Rev. 1.3
NXP Semiconductors 283
NOTE
Register bits PCLKAB0 to PCLKAB7 can be written anytime. If a clock
select is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
The clock source of each PWM channel is determined by PCLKx bits in PWMCLK (see Section 9.3.2.3,
“PWM Clock Select Register (PWMCLK) ) and PCLKABx bits in PWMCLKAB as shown in Table 9-5
and Table 9-6 .
9.3.2.8 PWM Scale A Register (PWMSCLA)
PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is
generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two.
Clock SA = Clock A / (2 * PWMSCLA)
Table 9-11. PWMCLK Field Descriptions
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero
Field Description
7
PCLKAB7
Pulse Width Channel 7 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 7, as shown in Table 9-6 .
1 Clock A or SA is the clock source for PWM channel 7, as shown in Table 9-6 .
6
PCLKAB6
Pulse Width Channel 6 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 6, as shown in Table 9-6 .
1 Clock A or SA is the clock source for PWM channel 6, as shown in Table 9-6 .
5
PCLKAB5
Pulse Width Channel 5 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 5, as shown in Table 9-5 .
1 Clock B or SB is the clock source for PWM channel 5, as shown in Table 9-5 .
4
PCLKAB4
Pulse Width Channel 4 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 4, as shown in Table 9-5 .
1 Clock B or SB is the clock source for PWM channel 4, as shown in Table 9-5 .
3
PCLKAB3
Pulse Width Channel 3 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 3, as shown in Table 9-6 .
1 Clock A or SA is the clock source for PWM channel 3, as shown in Table 9-6 .
2
PCLKAB2
Pulse Width Channel 2 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 2, as shown in Table 9-6 .
1 Clock A or SA is the clock source for PWM channel 2, as shown in Table 9-6 .
1
PCLKAB1
Pulse Width Channel 1 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 1, as shown in Table 9-5 .
1 Clock B or SB is the clock source for PWM channel 1, as shown in Table 9-5 .
0
PCLKAB0
Pulse Width Channel 0 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 0, as shown in Table 9-5 .
1 Clock B or SB is the clock source for PWM channel 0, as shown in Table 9-5 .