NXP Semiconductors MC9S12VRP64, Owner Reference Manual

Page: 163 / 555

S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V8)
MC9S12VRP Family Reference Manual Rev. 1.3
NXP Semiconductors 163
Depending on the COP configuration there might be a significant latency time until COP is active again
after exit from Stop Mode due to clock domain crossing synchronization. This latency time occurs if COP
clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for details).
Table 4-33 gives an overview of the COP condition (run, static) in Stop Mode depending on legal
configuration and status bit settings:
Table 4-33. COP condition (run, static) in Stop Mode
Three control bits in the CPMUCOP register allow selection of seven COP time-out periods.
When COP is enabled, the program must write $55 and $AA (in this order) to the CPMUARMCOP
register during the selected time-out period. Once this is done, the COP time-out period is restarted. If the
program fails to do this and the COP times out, a COP reset is generated. Also, if any value other than $55
or $AA is written, a COP reset is generated.
Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to
the CPMUARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out
period. A premature write will immediately reset the part.
In MCU Normal Mode the COP time-out period (CR[2:0]) and COP window (WCOP) setting can be
automatically pre-loaded at reset release from NVM memory (if values are defined in the NVM by the
application). By default the COP is off and no window COP feature is enabled after reset release via NVM
memory. The COP control register CPMUCOP can be written once in an application in MCU Normal
Mode to update the COP time-out period (CR[2:0]) and COP window (WCOP) setting loaded from NVM
memory at reset release. Any value for the new COP time-out period and COP window setting is allowed
COPOSCSEL1 CSAD PSTP PCE COPOSCSEL0 OSCE UPOSC COP counter behavior in Stop Mode
(clock source)
1 0 x x x x x Run (ACLK)
1 1 x x x x x Static (ACLK)
0 x 1 1 1 1 1 Run (OSCCLK)
0 x 1 1 0 0 x Static (IRCCLK)
0 x 1 1 0 1 x Static (IRCCLK)
0 x 1 0 0 x x Static (IRCCLK)
0 x 1 0 1 1 1 Static (OSCCLK)
0 x 0 1 1 1 1 Static (OSCCLK)
0 x 0 1 0 1 x Static (IRCCLK)
0 x 0 1 0 0 0 Static (IRCCLK)
0 x 0 0 1 1 1 Satic (OSCCLK)
0 x 0 0 0 1 1 Static (IRCCLK)
0 x 0 0 0 1 0 Static (IRCCLK)
0 x 0 0 0 0 0 Static (IRCCLK)