NXP Semiconductors MC9S12VRP64, Owner Reference Manual

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S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V8)
MC9S12VRP Family Reference Manual Rev. 1.3
NXP Semiconductors 161
4.5.2 Description of Reset Operation
Upon detection of any reset of Table 4-31 , an internal circuit drives the RESET pin low for 512 PLLCLK
cycles. After 512 PLLCLK cycles the RESET pin is released. The reset generator of the
S12CPMU_UHV_V8 waits for additional 256PLLCLK cycles and then samples the RESET pin to
determine the originating source.
Table 4-32 shows which vector will be fetched.
NOTE
While System Reset is asserted the PLLCLK runs with the frequency
f
VCORST
.
PLL Clock Monitor Reset None
Oscillator Clock Monitor Reset OSCE=1 in CPMUOSC register and
OMRE=1 in CPMUOSC2 register
COP Reset CR[2:0] in CPMUCOP register
Table 4-32. Reset Vector Selection
Sampled RESET Pin
(256 cycles after
release)
Oscillator monitor
fail pending
COP
time-out
pending Vector Fetch
1 0 0 POR
LVR
Illegal Address Reset
PLL Clock Monitor Reset
External pin RESET
1 1 X Oscillator Clock Monitor Reset
1 0 1 COP Reset
0 X X POR
LVR
Illegal Address Reset
PLL Clock Monitor Reset
External pin RESET
Table 4-31. Reset Summary
Reset Source Local Enable