NXP Semiconductors MC9S12VRP64, Owner Reference Manual

Page: 44 / 555

Device Overview S12VRP-Series
MC9S12VRP Family Reference Manual Rev. 1.3
44 NXP Semiconductors
1.12.2 ADC Special Conversion Channels
Whenever the ADC’s Special Channel Conversion Bit (SC) in ATD Control Register 5 (ATDCTL5) is set,
it is capable of running conversion on a number of internal channels.
Table 1-12 lists the internal sources
which are connected to these special conversion channels.
1.12.3 HVI Digital input enables
The HVI digital input enables of the MC9S12VRP-Series are controlled by the Port L DIENL register. The
corresponding ADC digital input enable bits in ATDDIENx are redundant.
1.12.4 API external clock output (API_EXTCLK)
The API_EXTCLK option which is described 4.3.2.15 Autonomous Periodical Interrupt Control Register
(CPMUAPICTL) is available on PT2.
1.12.5 COP Configuration
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are
loaded from the Flash configuration field byte at global address 0x3_FF0E during the reset sequence. See
Table 1-13 and Table 1-14 for coding.
Table 1-12. Usage of ADC Special Conversion Channels
ATDCTL5 Register Bits Usage
SC CD CC CB CA ADC Channel
1 0 0 0 1 Internal_7 Bandgap Voltage V
BG
or Chip temperature
sensor V
HT
see Section 4.3.2.13, “High
Temperature Control Register (CPMUHTCTL)
1 0 0 1 0 Internal_0 Flash Supply Voltage VDDF
1 1 0 1 0 Internal_4 V
SENSE
or V
SUP
selectable in BATS module see
Section 17.1.1 Features
Table 1-13. Initial COP Rate Configuration
NV[2:0] in
FOPT Register
CR[2:0] in
COPCTL Register
000 111
001 110
010 101
011 100
100 011
101 010
110 001
111 000