NXP Semiconductors MC9S12VRP64, Owner Reference Manual

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Port Integration Module (S12VRPPIMV1)
MC9S12VRP Family Reference Manual Rev. 1.3
NXP Semiconductors 77
2.3.4.4 Port L ADC Connection Enable Register (PTAENL)
6
OCIFP0
Over-Current Interrupt Flag —
This flag asserts if an over-current condition is detected on PP0 (Section 2.4.7.3, “Over-Current Interrupt and
Protection ”). Writing a logic “1” to the corresponding bit field clears the flag.
1 PP0 over-current event occurred
0 No PP0 over-current event occurred
5-0
PIFP5-0
Port Interrupt Flag — Signal pin event (KWU)
This flag asserts after a valid active edge was detected on the related pin (see Section 2.4.7.2, “Pin Interrupts and
Key-Wakeup (KWU) ”). This can be a rising or a falling edge based on the state of the polarity select register. An
interrupt will occur if the associated interrupt enable bit is set.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred
0 No active edge occurred
Address 0x0265 Access: User read/write
1
1
Read: Anytime
Write: Anytime
7 6 5 4 3 2 1 0
R 0 0
PTAENL5 PTAENL4 PTAENL3 PTAENL2 PTAENL1 PTAENL0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-24. Port L ADC Connection Enable Register (PTAENL)
Table 2-30. PTAENL Register Field Descriptions
Field Description
5-0
PTAENL
5-0
Port L ADC Connection Enable —
These bits enable the analog signal link to an ADC channel. If set to 1 the analog input function takes precedence
over the digital input in run mode by disabling the input buffer unless overridden by PTTEL=1.
Note: When enabling the resistor paths to ground by setting PTAENL=1, a delay of t
UNC_HVI
+ two bus cycles must
be accounted for.
1 ADC connection enabled
0 ADC connection disabled
Table 2-29. PIFP Register Field Descriptions (continued)
Field Description