NXP Semiconductors MC9S12VRP64, Owner Reference Manual

Page: 84 / 555

Port Integration Module (S12VRPPIMV1)
MC9S12VRP Family Reference Manual Rev. 1.3
84 NXP Semiconductors
Figure 2-33. Illustration of I/O pin functionality
The general-purpose data direction configuration can be overruled by an enabled peripheral function
shared on the same pin (
Table 2-40 ). If more than one peripheral function is available and enabled at the
same time, the highest ranked module according the predefined priority scheme in the tables of
Section 2.2, External Signal Description will take precedence on the pin.
Table 2-40. Effect of Enabled Features
Enabled Feature
1
1
If applicable the appropriate routing configuration must be set for the signals to take effect on the pins.
Related Signal(s) Effect on I/O state
CPMU OSC EXTAL, XTAL CPMU takes control
TIMx output compare y IOCx_y Forced output
TIMx input capture y IOCx_y None
2
2
DDR maintains control
SCIx TXDx SCI takes control
RXDx Forced input
PWM channel x PWMx Forced output
ADC channel x ANx None
2 3
3
To use the digital input function the related bit in Digital Input Enable Register (DIENAD) must be set to logic
level “1”.
AMPx AMPx, AMPPx, AMPMx None
2
IRQ IRQ Forced input
XIRQ XIRQ Forced input
LINPHY LPTXD Forced input
LPRXD, LPDR1 Forced output
PTx
DDRx
output enable
port enable
1
0
1
0
Pin
data out
Periph.
data in
Module
1
0
synch.
PTIx