NXP Semiconductors MC9S12VRP64, Owner Reference Manual

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Port Integration Module (S12VRPPIMV1)
MC9S12VRP Family Reference Manual Rev. 1.3
NXP Semiconductors 69
• Pull-device availability, pull-device polarity, wired-or mode, key-wake up functionality are
independent of the prioritization unless noted differently.
NOTE
This is a generic description of the standard PIM registers. For availability
of individual bits refer to
Section 2.3.1, “Register Map ” and Table 2-39
2.3.3.1 Port Data Register
2.3.3.2 Port Input Register
Address 0x0008 PTE
0x0271 PT1AD
0x0258 PTP
0x0248 PTS
0x0240 PTT
Access: User read/write
1
1
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
7 6 5 4 3 2 1 0
R
PTx7 PTx6 PTx5 PTx4 PTx3 PTx2 PTx1 PTx0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-11. Port Data Register
Table 2-18. Port Data Register Field Descriptions
Field Description
7-0
PTx7-0
Port Data — General purpose input/output data
This register holds the value driven out to the pin if the pin is used as a general purpose output.
When not used with the alternative function (refer to
Table 2-10 ), these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Address 0x0273 PTI1AD
0x0259 PTIP
0x0249 PTIS
0x0241 PTIT
Access: User read only
1
1
Read: Anytime
Write:Never
7 6 5 4 3 2 1 0
R PTIx7 PTIx6 PTIx5 PTIx4 PTIx3 PTIx2 PTIx1 PTIx0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-12. Port Input Register