UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
88 of 362
NXP Semiconductors
UM10208
Chapter 8: LPC2800 EMC
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If the buffers are enabled and the read data is contained in one of the buffers, the read
data is provided directly from the buffer.
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If the read data is not contained in a buffer, the LRU buffer is selected. If the buffer is
dirty (contains write data), the write data is flushed to memory. When an empty buffer
is available the read command is posted to the memory.
A buffer filled by performing a read from memory is marked as not-dirty (not containing
write data) and its contents are not flushed back to the memory controller unless a
subsequent AHB transfer performs a write that hits the buffer.
6.
Low-power operation
In many systems, the contents of the memory system have to be maintained during
low-power sleep modes. The EMC provides a mechanism to place the dynamic memories
into self-refresh mode.
Self-refresh mode can be entered by software by setting the SREFREQ bit in the
EMCDynamicControl Register and polling the SREFACK bit in the EMCStatus Register.
Any transactions to memory that are generated while the memory controller is in
self-refresh mode are rejected and an error response is generated to the AHB bus.
Clearing the SREFREQ bit in the EMCDynamicControl Register returns the memory to
normal operation. See the memory data sheet for refresh requirements.
Note: Static memory can be accessed normally when the SDRAM memory is in
self-refresh mode.
6.1 Low-power SDRAM Deep-sleep mode
The EMC supports JEDEC low-power SDRAM deep-sleep mode. Deep-sleep mode can
be entered by setting the deep-sleep mode (DP) bit in the EMCDynamicControl Register.
The device is then put into a low-power mode where the device is powered down and no
longer refreshed. All data in the memory is lost.
6.2 Low-Power SDRAM partial array refresh
The EMC supports JEDEC low-power SDRAM partial array refresh. Partial array refresh
can be programmed by initializing the SDRAM memory device appropriately. When the
memory device is put into self-refresh mode only the memory banks specified are
refreshed. The memory banks that are not refreshed lose their data contents.
7.
Memory bank select
The LPC288x provides four independently-configurable memory chip selects:
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Pins STCS2 through STCS0 are used to select static memory devices.
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Pins DYCS is used to select dynamic memory devices.
Static memory chip select ranges are each 2 megabytes in size, while the dynamic
memory chip select covers a range of 64 megabytes.
ranges of the chip selects.
