UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
125 of 362
NXP Semiconductors
UM10208
Chapter 9: LPC2800 Interrupt controller
SUBS pc, lr, #4
the SPSR_IRQ is restored to the CPSR with the I bit and F bit set, and therefore execution
will continue with all interrupts disabled. However, this can cause problems in the
following cases:
Problem 1:
A particular routine may be called as an IRQ handler, or as a regular
subroutine. In the latter case, the calling code disables interrupts before it calls the
subroutine. The routine exploits this restriction to determine how it was called, by
examining the I bit of the SPSR, and returns using the appropriate instruction. If the
routine is entered due to an IRQ being received during execution of the MSR instruction
which disables IRQs, the I bit in the SPSR would be set, and the routine would therefore
assume that it could not have been entered via an IRQ.
Problem 2:
FIQs and IRQs are both disabled by the same write to the CPSR. In this case,
if an IRQ is received during the CPSR write, FIQs will be disabled for the execution time of
the IRQ handler. This may not be acceptable in a system where FIQs must not be
disabled for more than a few cycles.
6.2 Workaround
There are 3 suggested workarounds. Which of these is most applicable will depend upon
the requirements of the particular system.
6.2.1 Solution 1: Test for an IRQ received during a write to disable IRQs
Add code similar to the following at the start of the interrupt routine.
SUB lr, lr, #4 ; Adjust LR to point to return
STMFD sp!, {..., lr} ; Get some free regs
MRS lr, SPSR ; See if we got an interrupt while
TST lr, #I_Bit ; interrupts were disabled.
LDMNEFD sp!, {..., pc}^ ; If so, just return immediately.
; The interrupt will remain pending since we haven’t
; acknowledged it and will be reissued when interrupts
; are next enabled.
; Rest of interrupt routine
This code will test for the situation where the IRQ was received during a write to disable
IRQs. If this is the case, the code returns immediately - resulting in the IRQ not being
acknowledged (cleared), and further IRQs being disabled.
Similar code may also be applied to the FIQ handler, in order to resolve the first issue.
This is the recommended workaround, as it overcomes both problems mentioned above.
However, in the case of problem two, it does add several cycles to the maximum length of
time FIQs will be disabled.
6.2.2 Solution 2: Disable IRQs and FIQs using separate writes to the CPSR
MRS r0, cpsr
ORR r0, r0, #I_Bit ;disable IRQs
MSR cpsr_c, r0
ORR r0, r0, #F_Bit ;disable FIQs
MSR cpsr_c, r0
