NXP Semiconductors LPC2880, User Manual

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UM10208_2 © NXP B.V. 2007. All rights reserved.
User manual Rev. 02 — 1 June 2007 175 of 362
NXP Semiconductors
UM10208
Chapter 14: LPC2800 UART
4. Architecture
The architecture of the UART is shown in Figure 14–24 .
The receiver block, RX, monitors the serial input line, RXD, for valid input. The RX Shift
Register (RSR) assembles characters from RXD. After a valid character is assembled in
the RSR, it is passed to the RX Buffer Register FIFO.
The transmitter block, TX, accepts data written to the TX Holding Register FIFO (THR) in
the Tx FIFO. The TX Shift Register (TSR) takes characters from the Tx FIFO and
serializes them onto the serial output pin, TXD.
The Baud Rate Generator block, BRG, generates the clock used by the RX and TX
blocks. The BRG clock input source is the CGU, and the clock is divided by the divisor in
the DLL and DLM registers. This divided clock must be 16 times the bit (baud) rate.
The interrupt interface contains registers IER and IIR. The interrupt interface receives
several signals from the TX and RX blocks.
Status information from the TX and RX is stored in the LSR. Control information for the TX
and RX is stored in the LCR.