UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
198 of 362
NXP Semiconductors
UM10208
Chapter 16: LPC2800 I
2
C
6.3 I
2
C Status Register (I2STS - 0x8002 0804)
Most of the bits in this register are read-only, but some can be cleared by writing a 1 to
that bit position. For the latter kind of bits, writing a 0 has no effect.
Table 218. I
2
C Status Register (I2STS - 0x8002 0804)
Bit
Symbol Description
Reset
value
0
OCI
Operation Complete:
this bit is set when master transmission or
reception has emptied the Tx FIFO, and the last entry in the FIFO
indicated “send a Stop condition after this byte”. It is cleared by writing a
1 to this bit.
0
1
AFI
Arbitration Failure:
this bit is set when the I
2
C interface is sending a
byte in master mode, it has released SDA for a current 1-bit, and it
samples the bit low (0). This situation is defined as a loss of arbitration
for this I
2
C interface. This bit is cleared by writing a 1 to this bit.
0
2
NAI
No Acknowledge:
this bit is set when a byte sent is not acknowledged.
It is cleared when a byte is written to the master Tx FIFO.
0
3
DRMI
Master Data Request:
this bit is set when the master Tx FIFO is empty
and the I
2
C interface is in master mode and has not completed a frame.
(It is not set when the last entry in the Tx FIFO indicated that the
associated byte should be followed by a Stop condition.) The condition is
alleviated and this bit is cleared when software or a DMA controller writes
data to the I2TX register.
0
4
DRSI
Slave Data Request:
this bit is set when the slave Tx FIFO is empty and
the I
2
C interface is in slave mode and needs data to send. (It is not set
when transmission of a byte is not acknowledged by the master.) The
condition is alleviated and this bit is cleared when software writes data to
the I2TXS register
0
5
ACTIVE
Active:
this bit is set by a Start condition and is cleared by a Stop
condition.
0
6
SCL
This bit reflects the current state of the SCL line.
X
7
SDA
This bit reflects the current state of the SDA line.
X
8
RFF
Receive FIFO Full:
this bit is 1 if the Receive FIFO is full. If another byte
arrives when this is the case, the I
2
C interface interlocks the bus by
holding SCL low until software or a DMA channel reads the I2RX register,
which clears this bit.
0
9
RFE
Receive FIFO Empty:
this bit is 1 if the Receive FIFO is empty. A
well-written interrupt service routine will check this bit before reading the
I2RX register.
1
10
TFF
Transmit FIFO Full:
this bit is 1 if the Tx FIFO is full. It is cleared when
the transmitter takes the next byte out of the FIFO.
0
11
TFE
Transmit FIFO Empty:
this bit is 1 if the Tx FIFO is empty. It is cleared
when software or a DMA channel writes a byte to the I2TX register.
1
12
TFFS
Slave Transmit FIFO Full:
this bit is 1 if the slave Tx FIFO is full. If is
cleared when the transmitter takes the next byte out of the FIFO.
0
13
TFES
Slave Transmit FIFO Empty:
this bit is 1 if the slave Tx FIFO is empty. If
is cleared when software writes a byte to the I2TXS register.
1
31:14 -
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
-