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UM10208_2

© NXP B.V. 2007. All rights reserved.

User manual

Rev. 02 — 1 June 2007

278 of 362

NXP Semiconductors

UM10208

Chapter 22: LPC2800 DDAC

19

SMUTE

After this bit is switched from 0 to 1, the gain of the interpolator is
gradually decreased (according to a raised cosine function) during
128 fs periods. When the output is fully muted, the voltage on the
output pins is (VREFN + VREFP)/2, and the MUTE bit in the
DDACSTAT register is set to 1. When this bit is switched from 1 to 0
(and after the output voltage has been ramped up to (VREFN +
VREFP)/2 after a Reset or when the PD bit is cleared), the gain of the
interpolator is gradually increased to the values indicated by the
RGAIN and LGAIN fields, during 128 fs periods.

0

21:20 MODE2FS

00 in this field selects 1 fs mode. Use this value if the input data rate is
between 8 kHz and 96 kHz and sharp filter roll-off is desired. In this
mode, all stages of the interpolation filter are used and digital
de-emphasis can be selected.
01 in this field selects 2 fs mode. Use this value if the input data rate is
96 kHz or above, and/or a slow roll-off is desired. In this mode, the
first stage of the interpolation filter is bypassed and digital
de-emphasis cannot be done.

0

23:22 ROLLOFF

The field controls sharp vs. slow rolloff. See

for allowed

combinations of values in this field and the MODE field. Do not
program combinations other than those shown.

0

24

PSLOW

This field controls how long the Dual DAC takes to power up and
down. 0 selects 512 fs periods; 1 selects 1024 fs periods.

0

25

DDAC_PD

A 1 in this bit powers down the interpolator. Setting this bit (as
described in

Section 22–6.3 “Power-down procedure” on page 282

automatically invokes the same soft-muting operation described
above for the SMUTE bit. Thereafter, the analog outputs are gradually
reduced to VREFN, in either 512 or 1024 fs periods, depending on the
PSLOW bit.
When this bit is switched from 1 to 0 (as described in

Section 22–6.2

“Power-up procedure” on page 282

) the analog outputs are gradually

increased from VREFN to (VREFN+VREFP)/2, in 512 or 1024 fs
periods depending on PSLOW. If bit SMUTE is 0, this voltage ramp
sequence is followed by a soft-unmute sequence as described above
for the SMUTE bit.

0

26

DDAC_INV A 1 in this bit inverts the signal polarity of both the left and right

channels.

28:27 SILDET_T

If the ENSILDET bit is 1, this field controls how many consecutive
all-zero input values each channel’s silence-detection circuit will
require, before it sets the LSILENT or RSILENT bit in the DDACSTAT
register.
00 3200
01 4800
10 9600
11 19200

29

ENSILDET A 1 in this bit enables the silence-detection circuit.

31:30 -

Reserved. Always write 0s to these bits. The value read from reserved
bits is not defined.

Table 315. Dual DAC Control Register (DDACCTRL - 0x8020 0398)

Bit(s) Name

Description

Reset
Value

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276
277
278
279
280
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Summary of Contents for LPC2880

Page 1: ...LPC2880 LPC2888 User manual Rev 02 1 June 2007 User manual Document information Info Content Keywords LPC2880 LPC2888 LPC288x ARM ARM7 embedded 32 bit microcontroller USB 2 0 USB HS Abstract LPC288x User manual ...

Page 2: ...operation Section 7 5 USB Device controller DMA mode transfer section was improved Section 17 6 4 Endpoint configuration table added Table 17 232 Section 17 8 6 on interrupt handling was further elaborated I O pinning Section 25 2 5 Pin structure added DC to DC converter Section 6 2 General operation was improved SD MMC interface Status register contents were corrected Table 23 345 Descriptions on...

Page 3: ...allow simultaneous GP DMA USB DMA and program execution from on chip Flash without contention External memory controller supports Flash SRAM ROM and SDRAM Advanced Vectored Interrupt Controller supporting up to 30 vectored interrupts Innovative Event Router allows interrupt power up and clock start capabilities from up to 105 sources Multi channel GP DMA controller that can be used with most on ch...

Page 4: ...he ARM architecture is based on Reduced Instruction Set Computer RISC principles and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers This simplicity results in a high instruction throughput and impressive real time interrupt response from a small and cost effective processor core Pipeline techniques are employed so t...

Page 5: ...ram the Flash while the application is running allowing a great degree of flexibility for data storage and field firmware upgrades The Flash is 128 bits wide and includes buffering to allow 3 out of 4 sequential read operations to operate without wait states 7 On Chip Static RAM The LPC288x includes 64 kB of static RAM that may be used for code and or data storage 8 On Chip ROM The LPC288x include...

Page 6: ...2I X32O CLOCK GENERATION UNIT OSCILLATOR AND PLLs ARM7TDMI S JTAG DEBUG INTERFACE 8 kB CACHE JTAG_TRST JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_SEL FLASH INTERFACE 1 MB FLASH 1 SRAM INTERFACE 64 kB SRAM ROM INTERFACE BOOT ROM REAL TIME CLOCK OSCILLATOR FIFO FIFO I2S BUS INPUT FIFO I2S BUS OUTPUT DUAL ANALOG INPUT FIFO DUAL ANALOG OUTPUT EXTERNAL MEMORY CONTROLLER A 20 0 D 15 0 etc VECTORED INTERRU...

Page 7: ...Address range details and description 0x0000 0000 to 0x0FFF FFFF Cacheable area 0x0020 0000 0x0020 7FFF Internal ROM 32 kB 0x0040 0000 0x0040 FFFF Internal RAM 64 kB other addresses Software can map other internal and external memory into this area to improve its effective access time 0x1000 0000 to 0x1FFF FFFF Internal Memory 0x1040 0000 0x104F FFFF Flash 1 MB 0x2000 0000 to 0x5FFF FFFF External ...

Page 8: ...FFF FFFF internal ROM 32 kB 0x0020 0000 to 0x0020 7FFF reserved 0x0050 0000 to 0x0FFF FFFF internal RAM 64 kB 0x0040 0000 to 0x0040 FFFF reserved 0x2020 0000 to 0x23FF FFFF internal flash 1 MB 0x1040 0000 to 0x104F FFFF reserved 0x1000 0000 to 0x0000 003F reserved 0x2820 0000 to 0x2FFF FFFF reserved 0x3400 0000 to 0x3FFF FFFF static memory bank 2 2 MB 0x4800 0000 to 0x481F FFFF reserved 0x4420 000...

Page 9: ...FF AHB 0x8000 8000 0x8000 8258 External Memory Controller EMC 0x8002 0000 0x8000 03FF APB1 0x8002 0000 0x8002 0010 Timer 0 0x8002 0400 0x8000 07FF APB1 0x8002 0400 0x8002 0410 Timer 1 0x8002 0800 0x8002 0BFF APB1 0x8002 0800 0x8002 082C I2C Controller 0x8004 0000 0x8004 1FFF AHB 0x8004 0000 0x8004 10B4 USB Controller 0x8010 0000 0x8010 0FFF APB2 0x8010 0000 0x8010 00BC Secure Digital Multimedia Ca...

Page 10: ...each boot mode in more detail Mode 0 Execute user program from internal flash memory This is the default mode if the P2 3 and P2 2 pins are left unconnected The Flash memory begins at address 0x1040_0000 This is the address branched to in this mode In order to prevent accidental execution of an unprogrammed Flash the ROM code checks for a specific valid user program marker value in memory prior to...

Page 11: ... The starting address used for the external static memory is 0x2000_0000 The full address range for bank 0 is 0x4000_0000 through 0x401F_FFFF a 2 megabyte space Mode 2 Download program from USB port to memory DFU mode The purpose of this mode is to allow programming of the internal Flash memory via USB Files to be download must be specially formatted in order to be handled by the ROM download code...

Page 12: ... contains a value that identifies this device Fig 3 Boot process Basic Initialization disable interrupts disable cache initialize CGU Initialize exception modes Mode 3 Y N Initialize external memory controller Mode 1 Y N Mode 2 Y N Initialize internal memory systems Reset Continuously toggle pin P2 1 Branch to first Flash address USB download Branch to first bank 0 address Flash ready N Valid User...

Page 13: ...ual Rev 02 1 June 2007 13 of 362 NXP Semiconductors UM10208 Chapter 3 LPC2800 Boot process Table 4 Part Identification register SYS_PARTID 0x8000 507C Bit Symbol Description Reset value 31 0 PART_ID This value distinguishes this device type 0x0102 100A ...

Page 14: ...secutive 32 bit words The cache contains 128 cache lines each with 2 ways making 8 kB total The association of memory addresses to cache lines is that cache line 0 corresponds with address word addresses 0x0 to 0x07 cache line 1 corresponds with word addresses 0x08 to 0x0F etc After 1024 words this repeats Thus word address 0 word address 1024 word address 2048 all map to cache line 0 A tag word i...

Page 15: ... stored on the first cache line cache line 0 of Way_0 An access to one of the second 8 words in the same page will be stored on the second cache line cache line 1 of Way_0 Later if an address that maps to cache line 0 is read from a different portion of memory it will be stored in Way_1 since Way_1 has not yet been used If still another address mapping to cache line 0 is read the Least Recently Us...

Page 16: ...apping is given On the left of the diagram memory is shown with no remapping as issued by the CPU On the right a higher physical address is shown mapped into a lower address for caching purposes To accomplish this a page is used as a virtual page Accessing this virtual page the cache will re map the AHB bus address to the higher address range during a cache miss cache flush or a write access to th...

Page 17: ...so be accessed directly by the CPU using the original absolute address of the page In that case the cache takes no part in the access This allows both cached and non cached access to the same address region if needed Each of the 16 configurable cache pages can be individually enabled and disabled as well as having a virtual address programmed Fig 5 Memory mapping 0x0000_0000 0x0020_0000 0x0040_000...

Page 18: ...rded because of a cache miss the cache line needs to be reused for a different memory region the old line is first written back to memory a cache line flush When a cache line is read from memory and stored in the cache in Way_0 or Way_1 the cache controller will mark the other half of the cache line at the same address as Least Recently Used LRU in its tag memory 5 Register description The cache c...

Page 19: ...oints this page to the on chip SRAM 0x2 R W 0x8010 4024 PAGE_ADDRESS_3 Re mapping address for page 3 The reset value points this page to the on chip SRAM 0x2 R W 0x8010 4028 PAGE_ADDRESS_4 Re mapping address for page 4 The reset value points this page to on chip Flash memory 0x82 R W 0x8010 402C PAGE_ADDRESS_5 Re mapping address for page 5 The reset value points this page to external static memory...

Page 20: ...ption Reset value 0 CACHE_RST Cache controller reset control This bit resets the cache hardware internally clearing all tags so that the entire cache is considered empty This takes 128 CPU clock cycles to complete The reset progress can be followed by reading register CACHE_RST_STAT 0 De assert reset to the Flash controller 1 Assert reset to the Flash controller Note the cache MUST be reset before...

Page 21: ... CACHE_SETTINGS 0x8010 4004 Bit Symbol Description Reset value Table 8 Cache Page Enable Control register CACHE_PAGE_CTRL 0x8010 4008 Bit Symbol Description Reset value 0 PAGE_0_ENA This bit enables caching for page 0 0 Caching for this page is disabled 1 Caching for this page is enabled 0 1 PAGE_1_ENA This bit enables caching for page 1 as described for bit 0 0 2 PAGE_2_ENA This bit enables cachi...

Page 22: ...not actually being used 5 6 Cache Write Misses counter C_WR_MISSES 0x8010 4014 The C_WR_MISSES register allows reading the number of times that a write has occurred to a memory address that is not in the cache a cache write miss The counter only operates if performance analysis has been enabled via the PERF_ANAL_ENA bit in the CACHE_SETTINGS register In order to save power performance analysis sho...

Page 23: ...e Bottom of related address range Top of related address range PAGE_ADDRESS_0 0 0x0000 0000 0x001F FFFF PAGE_ADDRESS_1 1 0x0020 0000 0x003F FFFF PAGE_ADDRESS_2 2 0x0040 0000 0x005F FFFF PAGE_ADDRESS_3 3 0x0060 0000 0x007F FFFF PAGE_ADDRESS_4 4 0x0080 0000 0x009F FFFF PAGE_ADDRESS_5 5 0x00A0 0000 0x00BF FFFF PAGE_ADDRESS_6 6 0x00C0 0000 0x00DF FFFF PAGE_ADDRESS_7 7 0x00E0 0000 0x00FF FFFF PAGE_ADDR...

Page 24: ... be put on the AHB bus This allows any part of the entire 32 bit address range to be remapped into the bottom 32 megabytes of space in pages of 2 megabytes The PAGE_ADDRESS registers DO NOT reset to a value such that remapping is not in force so they should always be initialized even if remapping is not needed in the application Example Say address location 0x10400000 in on chip Flash must be mapp...

Page 25: ...s to guarantee that the data inside the cache is written to memory the programmer has to flush the cache The cache controller does not include a direct method to cause an immediate cache flush If software needs to flush the entire cache a simple way to accomplish this is to fill the cache with read only data for instance ROM data This results in every cache line being checked to see if it is dirty...

Page 26: ...cheable Data written to the non cached page is written directly to memory so other bus masters can make use of this data without any need to flush the cache Care must be taken not to write data to one page and read the same data from the other page This can be done by separating portions of the page that may be changing from portions that will not be changing Changeable portions would be both read...

Page 27: ...s generated by the cache when the CPU must wait because either the cache is reading or writing data on the AHB bus or the cache is jumping in between cache lines adding a single wait state Fig 6 Cache and CPU clock timing CPU clock AHB0 clock Internal cache clock Internal CPU clock CPU clock enable Case 1 CPU clock gating off fractional divider not used CPU clock AHB0 Clock Internal cache clock In...

Page 28: ...ad operation These four words of data are referred to as a flash word During programming four flash words are programmed at a time 3 2 Flash buffering Because the Flash memory is 128 bits wide while the AHB is a 32 bit interface a buffer between the Flash memory and the AHB can reduce power by limiting the number of Flash reads required as well as speed up response to reads of consecutive Flash lo...

Page 29: ...tor 2 64KB large sector 1 64KB large sector 0 8KB small sector 5 8KB small sector 4 8KB small sector 3 8KB small sector 2 8KB small sector 1 8KB small sector 0 8KB small sector 6 0x1040_0000 to 0x1040_FFFF 0x1041_0000 to 0x1041_FFFF 0x1042_0000 to 0x1042_FFFF 0x1043_0000 to 0x1043_FFFF 0x1048_0000 to 0x1048_FFFF 0x1047_0000 to 0x1047_FFFF 0x1046_0000 to 0x1046_FFFF 0x1045_0000 to 0x1045_FFFF 0x104...

Page 30: ...r value just after decreasing the CPU clock rate 4 In Application flash programming 4 1 Introduction Programming the embedded flash memory requires a specific sequence of events controlled primarily by software The flash memory is organized in sectors as shown in Figure 5 7 that must be erased before data can be written into them The flash memory also has built in protection against accidental pro...

Page 31: ...d upon 2 Erasing sectors that have been previously programmed 3 Presetting data latches for each flash word to be programmed 4 Writing 5 Loading 6 Programming Fig 8 Flash AHB programming flow chart Un Protect sector s Erase sector s Preset data latches Write Word auto Load Flash Load Flash Word Program Flash Page Protect sector s Flash Word complete Page complete Sector s complete Last Flash Word ...

Page 32: ...ime must satisfy the requirement 512 FPT_TIME 2 AHB clock time 400ms Which is to say write FPT_TIME with the integer greater than or equal to 400 000 000 AHB tcyc in ns 2 512 A single sector is erased by writing any value to an address within that sector followed by writing the erase trigger value to the F_CTRL register The trigger value for erasing has the following bits set FC_PROG_REQ FC_PROTEC...

Page 33: ...done per Flash Word For example when addresses 0x00 through 0x0C are to be loaded loading is done automatically after writing to address 0x0C note that these four addresses form a single complete Flash Word This requires that values are already written to addresses 0x00 to 0x08 Loading can also be done manually by writing a 1 to the FC_LOADREQ bit in the F_CTRL register 4 6 Programming First a sec...

Page 34: ...are stalled using AHB wait states Writes to the flash controller registers are stalled Reads of flash controller registers are completed normally without stalling This can have significant impact on system behavior It should be insured that the Flash memory is not busy the FPT_TIME field in the F_PROG_TIME register 0 and the FS_RDY bit in the F_STAT register 1 prior to attempting to read Flash dat...

Page 35: ...active mode R W 1 1 FC_FUNC Program erase selection 0 select erase 1 select program data load R W 0 2 FC_WEN Program erase enable 0 enable program erase 1 disable program erase R W 1 4 3 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 5 FC_RD_LATCH Selects reading of Flash data or Flash data latch value 0 read Flash array 1 read data ...

Page 36: ...the load register R W 0 31 16 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 13 Flash Control register F_CTRL 0x8010 2000 Bits Name Description Access Reset value Table 14 Flash Status register F_STAT 0x8010 2004 Bits Name Description Access Reset value 0 FS_DONE Programming cycle done 0 during program erase 1 total program era...

Page 37: ...ide 66 kHz prior to beginning programming or erase operations The fields in the F_CLK_TIME register are shown in Table 5 17 Table 15 Flash Program Time register F_PROG_TIME 0x8010 2008 Bits Name Description Access Reset value 14 0 FPT_TIME Programming timer Remaining program erase time is 512 FPT_TIME clock cycles R W 0 15 FPT_ENABLE Program timer Enable 0 timer disabled 1 timer enabled R W 0 31 1...

Page 38: ...ll cause an interrupt request to be generated if the corresponding enable bit in the F_INTEN register equals one and if the interrupt is enabled in the system interrupt controller Table 17 Flash Clock Divider register F_CLK_TIME 0x8010 201C Bits Name Description Access Reset value 11 0 CLK_DIV Clock divider setting 0x000 no programming clock is available to the Flash memory Other a programming clo...

Page 39: ...ctions The fields in the F_INTEN_SET register are shown in Table 5 22 Table 19 Flash Interrupt Set register F_INT_SET 0x8010 2FEC Bits Name Description Access Reset value 1 0 SET_INT These bits allow software setting of interrupt flag bits in the F_INT_STAT register 0 leave the corresponding bit unchanged 1 set the corresponding bit WO 31 2 Reserved user software should not write ones to reserved ...

Page 40: ...xecution from Flash see the Boot Process chapter the boot code waits for this status bit to be 0 before reading the valid program marker word from Flash The fields in the FLASH_INIT register are shown in Table 5 25 Table 22 Flash Interrupt Enable Set register F_INTEN_SET 0x8010 2FDC Bits Name Description Access Reset value 1 0 SET_ENABLE These bits allow software setting of interrupt enable bits i...

Page 41: ...r FLASH_INIT 0x8000 5034 Bits Name Description Access Reset value 0 FLASH_INIT Flash initialization status bit 0 If the Flash is not in Power Down mode it is ready for use 1 If the Flash is not in Power Down mode it is currently undergoing initialization RO 31 1 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined ...

Page 42: ...he voltage up to the needed levels Switching between the two modes is supported For example a handheld battery powered device can be plugged into a USB port and use that power while connected in order to save battery life For the sake of brevity the entire power regulation system is referred to as the DC DC converter UM10208 Chapter 6 DC to DC converter Rev 02 1 June 2007 User manual Fig 9 Block d...

Page 43: ...s that information to adjust the converters to keep the output voltage in range During the start up the DC DC Controller uses the Ring Oscillator to control the switching regulators After start up software may switch the DC DC clock to the 12 MHz crystal When operating from a battery supply the output voltage of DCDC_VDDO 3V3 and DCDC_VDDO 1V8 can be controlled by software This is done via 3 adjus...

Page 44: ...st of its pins should be tied to ground as shown in Figure 6 11 External power may be supplied from any suitable source Fig 10 Example application hookup for battery and USB power DCDC_VDDO 3v3 DCDC_VDDO 1v8 DCDC_VDDI 3v3 DCDC_VBAT DCDC_VUSB START STOP STOP START DCDC_GND DCDC_CLEAN DCDC_LX1 DCDC_LX2 DCDC_VSS1 DCDC_VSS2 LPC288x USB_VBUS BATTERY 3 3V BAT54C 10K 1K 22µF 10V L1 L2 1 8V L18 L17 N18 N1...

Page 45: ...ve edge at the START input activates the DC DC converter When minimum supply voltages are detected for DCDC_VDDO 3V3 and DCDC_VDDO 1V8 SUPPLY_OK becomes true After about 1 ms determined by a number of clock periods of the Ring Oscillator the internal active low reset signal is de asserted Once started additional edges on the START pin have no effect on the DC DC Converter The upper trace shows the...

Page 46: ..._VDDO 3V3 are combined for use with START and STOP switches 3 2 START and STOP from USB power Figure 6 13 shows the timing of the DC DC Converter while USB power is applied and removed Note that timing and voltage levels are not to scale Application of USB power when the device is not operating causes an automatic start up The internal reset remains asserted for about 1 ms after power becomes avai...

Page 47: ...tage levels are not to scale The figure shows the DC DC running due to a prior START from battery power USB power is then applied causing the DC DC converters to be turned off while power is switched to use the output of the LDO regulators USB power is always used preferentially if it is available When USB power is disconnected a STOP is generated and the device goes to the off state Fig 13 Intern...

Page 48: ...B supply and off STOP DCDC_VUSB DCDC_VBAT START DC DC output voltage may vary during the change from DC DC output to LDO output internal reset_n Supply_OK DC DC enable Between Stop and Start the device is in the idle mode supplies DCDC_VDDO 3V3 and DCDC_VDDO 1V8 are present but only a small current is required DCDC_VDDO 1V8 and DCDC_VDDO 3v3 Table 26 DC DC converter registers Name Size Description...

Page 49: ...ware should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 28 Adjustment range for DCDC converter 1 DCDCADJUST1 bits Low threshold Typical High threshold 000 3 562 3 636 3 710 001 3 406 3 477 3 548 010 3 250 3 318 3 385 011 3 094 3 159 3 223 100 2 938 2 999 3 306 101 2 782 2 840 2 898 110 2 626 2 681 2 735 111 2 470 2 522 2 573 Table 29 DCDC converter 2 ...

Page 50: ... 1 300 1 327 111 1 196 1 221 1 246 Table 30 Adjustment range for DCDC converter 2 DCDCADJUST1 bits Low threshold Typical High threshold Table 31 DCDC Clock Select register DCDCCLKSEL address 0x8000 500C Bit Symbol Description Reset value 0 DCDCCLKSEL This bit indicates to the DCDC converter block whether the ring oscillator or a 12 MHz clock source from the CGU should be used to control the DC DC ...

Page 51: ...e base clock pulse per their multiply divide period or can approximate a 50 50 duty cycle of their multiply divide period Software reset capability for each reset domain Each clock domain can have its clock disabled 2 Description The Clock Generation Unit generates clock and reset signals for the various modules of the LPC288x A block diagram of the CGU is shown in Figure 7 15 It includes 7 main c...

Page 52: ...own in Figure 7 16 The selection stages select among the main clocks although they are more complex than simple selectors in order to avoid glitches when they are being dynamically switched between main clocks The outputs of the selection stages are called base clocks Some selection stages and base clocks are dedicated to a particular spreading stage and Fig 15 Clock generation unit block diagram ...

Page 53: ...period or this pulse can be stretched to provide an approximate 50 50 duty cycle of the multiply divide period Finally an output of the Event Router block is used as a wakeup signal that globally enables the clocks for those spreading stages that are programmatically selected for such wakeup The clocks produced by the spreading stages are used to provide clock synchronized reset signals for the va...

Page 54: ...rk This read only bit is set by a Watchdog reset and cleared by a low on RESET Software can read it to determine which kind of reset has occurred 0 RESET 1 WDT 31 1 Reserved The value read from a reserved bit is not defined Table 35 32 kHz Oscillator Control OSC32EN 0x8000 4C08 Bit Symbol Description Reset value 0 When this bit is 1 as it is after a reset the 32 kHz oscillator runs 1 31 1 Reserved...

Page 55: ...in 0100 WSI pin 0111 High Speed PLL values not shown are reserved and should not be written R W 0001 0x8000 4CE4 LPPDN Power Down Register When bit 0 of this register is 1 as it is after a reset the main PLL is powered down Write a 0 to this bit after writing the LPMSEL and LPPSEL registers to start the main PLL R W 1 0x8000 4CE8 LPMBYP Multiplier Bypass Register When bit 0 of this register is 1 C...

Page 56: ...8000 4CF8 LPPSEL Division Factor If LPDBYP is 0 program this 2 bit register so that 160 MHz FCLKOUT 2 LPPSEL 1 320 MHz Note that 2 LPPSEL 1 2 4 8 or 16 R W 0 0x8000 4CFC Table 38 Main PLL Operating Modes LPMBYP LPDBYP Operation 0 0 Normal Mode The PLL output clock clkout is the selected input clock multiplied by LPMSEL 1 The post divider is used and the FCCO frequency is FCLKOUT 2 LPPSEL 1 which m...

Page 57: ... one combination remains after applying recommendation 1 choose combinations that don t involve initial division over those that do This minimizes phase noise and jitter 3 If more than one combination remains after applying recommendation 2 there are two possible approaches First a PLL oscillator frequency causes the PLL to consume less power For lower power operation choose the settings that give...

Page 58: ...lications Table 7 41 shows multiplier and divisor values that derive common frequencies from the Fast oscillator running at 12 MHz with the associated values for the HPNDEC HPMDEC HPPDEC HPSELR HPSELI and HPSELP registers All values are decimal Table 40 HS PLL Multiplication and Division Memory Tables Memory table Indexed by index bits output bits Write to register s Table size NTAB NSEL 8 10 HPND...

Page 59: ...of the HS PLL R W 0x004 0x8000 4CBC HPSTAT Status This register contains the status of the HP PLL RO 0 0x8000 4CC0 HPREQ Rate Change Request After dynamically changing any of the DEC or SEL values write to this register and then wait for the HPACK register to acknowledge the change R W 0 0x8000 4CC8 HPACK Rate Change Acknowledge After writing to HPREQ wait for this register to contain the value wr...

Page 60: ...elected so that the multiplied clock is between 275 and 550 MHz 0 31 17 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 46 Final Divider Control Register HPPDEC 0x8000 4CB8 Bit Symbol Description Reset value 6 0 PDEC The output of the HS PLL is the multiplied clock divided by even values between 2 and 64 inclusive The value writ...

Page 61: ...REQ After dynamically changing the PDEC register write a 1 to this bit wait for the PACK bit in HPACK to be set then clear this bit then wait for PACK to be 0 0 31 3 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 50 Rate Change Acknowledge Register HPACK 0x8000 4CC4 Bit Symbol Description Reset value 0 HPMACK After dynamically ...

Page 62: ...r more selection stages to use the high speed PLL as their clock input 3 7 2 Handshake procedure The steps above are simple enough to serve for reprogramming but there is an alternative that allows software to make rate changes more quickly than waiting for a complete power up 1 Write 0 to the SCRs of any selection stages that use the PLL to disable use of the PLL s output 2 For each of HPNSEL HPM...

Page 63: ...APB3SCR DCDCSCR RTCSCR MCISCR UARTSCR DAIOSCR DAISCR Switch Configuration Registers These 4 bit registers enable or disable the output of the selection stage select between the two sides of the stage and allow resetting the stage Some SCRs reset to 0001 running others to 1001 stopped R W x001 0x8000 4000 0x8000 4004 0x8000 4008 0x8000 400C 0x8000 4010 0x8000 4014 0x8000 4018 0x8000 401C 0x8000 402...

Page 64: ...AI BCLK pin 0100 DAI WS pin 0111 High Speed PLL 1000 Main PLL other values are reserved and should not be written 0001 31 4 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 57 Frequency Select 2 Registers SYSFSR2 DAIFSR2 0x8000 4058 407C Bit Symbol Description Reset value 3 0 SELECT This field selects the main clock for side 2 of...

Page 65: ... side After software completes step 3 the selection stage first disables the old main clock during its low time then waits one stage of the new main clock before driving its output from the new main clock This process prevents glitches minimum high or low time violations on the output base clock 3 10 Fractional divider registers Each of the 17 fractional dividers in the CGU includes the registers ...

Page 66: ... Register ESR Table 60 Fractional divider configuration registers Names Bit Symbol Description Reset value Addresses SYSFDCR0 SYSFDCR1 SYSFDCR2 SYSFDCR3 SYSFDCR4 SYSFDCR5 APB0FDCR0 APB0FDCR1 APB1FDCR APB3FDCR UARTFDCR DAIOFDCR0 DAIOFDCR1 DAIOFDCR2 DAIOFDCR3 DAIOFDCR4 DAIOFDCR5 0 FDRUN A 1 in this bit enables the fractional divider 0 0X8000 43FC 0X8000 4400 0X8000 4404 0X8000 4408 0X8000 440C 0X800...

Page 67: ...3PCR0 0x8000 40BC MMIOPCR0 0x8000 40C0 AHB0PCR 0x8000 40C4 MCIPCR0 0x8000 40C8 MCIPCR1 0x8000 40CC UARTPCR0 0x8000 40D0 1 0x8000 40D4 1 0x8000 40D8 FLSHPCR0 0x8000 40DC FLSHPCR1 0x8000 40E0 FLSHPCR2 0x8000 40E4 LCDPCR0 0x8000 40E8 LCDPCR1 0x8000 40EC DMAPCR0 0x8000 40F0 DMAPCR1 0x8000 40F4 USBPCR0 0x8000 40F8 CPUPCR0 0x8000 40FC CPUPCR1 0x8000 4100 CPUPCR2 0x8000 4104 RAMPCR 0x8000 4108 ROMPCR 0x8...

Page 68: ...his clock is enabled by a rising edge on wakeup and disabled when software writes 11 to the Mode field of the Power Mode Control register Table 7 33 on page 54 1 3 EXTEN_EN A 1 in this bit puts this clock under control of a signal from the target module or submodule On the LPC288x this feature is used for registers that have no dynamic operational aspects and the control signals are APB module sel...

Page 69: ...0 4234 APB0PSR1 0x8000 4238 EVRTPSR 0x8000 423C RTCPSR0 0x8000 4240 ADCPSR0 0x8000 4244 ADCPSR1 0x8000 4248 WDTPSR 0x8000 424C IOCPSR 0x8000 4250 CGUPSR 0x8000 4254 SYSCPSR 0x8000 4258 APB1PSR1 0x8000 425C T0PSR 0x8000 4260 T1PSR 0x8000 4264 I2CPSR 0x8000 4268 APB3PSR1 0x8000 426C SCONPSR 0x8000 4270 DAIPSR0 0x8000 4274 DAOPSR0 0x8000 427C SIOPSR 0x8000 4280 SAI1PSR 0x8000 4284 SAI4PSR 0x8000 4290...

Page 70: ... 0x8000 43C4 UARTESR1 0x8000 43C8 DDACESR1 0x8000 43CC DDACESR2 0x8000 43D0 DADCESR1 0x8000 43D4 DADCESR2 0x8000 43D8 DAIESR1 0x8000 43DC DAIESR2 0x8000 43E0 DAOESR1 0x8000 43E4 DAOESR2 0x8000 43E8 DAOESR3 0x8000 43EC Table 68 Enable select register bit descriptions Bit Symbol Description Reset value 0 ESR_EN A 0 in this bit causes the spreading stage output clock to be the same as the input clock...

Page 71: ...e 69 ESRs with ESR_SEL fields ESRs with 3 bit fields ESRs with 1 bit fields APB0ESR0 APB1ESR0 APB0ESR1 APB2ESR APB3ESR0 EVRTESR MMIOESR0 AHB0ESR0 RTCESR MCIESR0 MCIESR1 ADCESR0 UARTESR0 FLSHESR0 ADCESR1 FLSHESR1 FLSHESR2 WDTESR LCDESR0 LCDESR1 IOCESR DMAESR0 DMAESR1 CGUESR USBESR0 CPUESR0 SYSCESR CPUESR1 CPUESR2 RAMESR ROMESR EMCESR0 EMCESR1 MMIOESR1 DDACESR1 DDACESR2 DADCESR1 DADCESR2 DAIESR1 DAI...

Page 72: ...lumn describes what module s the clock is used in and how it s used MCIRES 0x8000 4C44 MCI FD interface MCIRES2 0x8000 4C48 MCI FD interface UARTRES 0x8000 4C4C UART I2CRES 0x8000 4C50 I2C interface SCONRES 0x8000 4C58 Streaming Configuration block DAIRES 0x8000 4C60 DAI DAORES 0x8000 4C68 DAO DADCRES 0x8000 4C6C Dual ADC EDGERES 0x8000 4C70 DAO Edge Detector DDACRES 0x8000 4C74 Dual DAC SAI1RES 0...

Page 73: ...terface MCIxxx1 MCI_MCLK MCI clock for MCI FD interface UARTxxx0 UART_PCLK APB clock for UART FLSHxxx0 FLASH_CLK main clock for Flash FLSHxxx1 FLASH_TCLK test clock for Flash FLSHxxx2 FLASH_PCLK PCLK for Flash LCDxxx0 LCD_PCLK PCLK for LCD interface LCDxxx1 LCD_CLK LCD bus clock for LCD interface DMAxxx0 DMA_PCLK PCLK for DMA channels DMAxxx1 DMA_GCLK gated register clock for DMA channels USBxxx0 ...

Page 74: ...DAO APB interface SIOxxx SIO_PCLK Stream I O clock used for I2S I O DADC DDAC SAI1xxx SAI1_PCLK clock for SAI1 SAI4xxx SAI4_PCLK clock for SAI4 SAO1xxx SAO1_PCLK clock for SAO1 SAO2xxx SAO2_PCLK clock for SAO2 DDACxxx0 DDAC_PCLK clock for Dual DAC APB interface EDGExxx EDGE_PCLK clock for DAO edge detector DADCxxx0 DADC_PCLK clock for Dual ADC APB interface DCDC DCDCxxx DCDC_CLK clock for DC DC Co...

Page 75: ...ion stages Fractional divider registers Spreading stage registers Clock name Clock description 32 kHz Osc 12 MHz Osc MCLK pin BCKI pin WSI pin Main PLL HS PLL SYS SYSFDCR0 SYSFDCR1 SYSFDCR2 SYSFDCR3 SYSFDCR4 SYSFDCR5 APB0xxx0 APB0_CLK APB1xxx0 APB1_CLK APB2xxx0 APB2_CLK APB3xxx0 APB3_CLK MMIOxxx0 MMIO_HCLK AHB clock for interrupt controller AHB0xxx AHB0_CLK MCIxxx0 MCI_PCLK PCLK for MCI FD interfa...

Page 76: ...llator as PLL s input clock LPMSEL 0x00000004 Multiply input clock by 4 1 5 LPPSEL 0x00000001 Make CCO equal to 4 times PLL output LPPDN 0x00000000 Power up the main PLL while LPLOCK 0x00000000 Wait for PLL to lock Selection Stage if SYSSSR CGU_FSR1 SYSFSR2 CGU_FSR_MAIN_PLL Select Main PLL as main clock SYSSCR SYSSCR 0xC CGU_FSR2 Enable side 2 else SYSFSR1 CGU_FSR_MAIN_PLL Select Main PLL as main ...

Page 77: ... FLSHESR0 0x0 The same as the SYS base clock FLSHESR1 0x0 The same as the SYS base clock FLSHESR2 0x0 The same as the SYS base clock LCDESR0 0x0 The same as the SYS base clock DMAESR0 0x0 The same as the SYS base clock DMAESR1 0x0 The same as the SYS base clock USBESR0 0x0 The same as the SYS base clock CPUESR0 0x0 The same as the SYS base clock CPUESR1 0x0 The same as the SYS base clock CPUESR2 0...

Page 78: ...er SYSFDCR0 i e 30 MHz The MCI_MCLK MCI clock for MCI SD Table 73 Structure of the CGU Main clocks Selection stages Fractional divider registers Spreading stage registers Clock name Clock description 32 kHz Osc 12 MHz Osc MCLK pin BCKI pin WSI pin Main PLL HS PLL SYS SYSFDCR0 SYSFDCR1 SYSFDCR2 SYSFDCR3 SYSFDCR4 SYSFDCR5 APB0xxx0 APB0_CLK APB1xxx0 APB1_CLK APB2xxx0 APB2_CLK APB3xxx0 APB3_CLK MMIOxx...

Page 79: ... 0x2 define CGU_FDCR_FDRUN 0x1 define CGU_FDCR_FDRES 0x2 define CGU_FDCR_FDSTRCH 0x4 define SYSFDCR0_MSUB 0xC0 define SYSFDCR0_MADD 0x40 define SYSFDCR1_MSUB 0xB0 define SYSFDCR1_MADD 0x70 define SYSFDCR3_MSUB 0xF0 define SYSFDCR3_MADD 0x90 define CGU_ESR_FD0 0x1 define CGU_ESR_FD1 0x3 define CGU_ESR_FD3 0x7 define CGU_ESR_FD5 0xB define CGU_PCR_ENOUT_EN 0x10 define CGU_BCR_FDRUN 0x1 Main PLL Setu...

Page 80: ...ivider Spreading stage Choose clocks for spreading stages under SYS APB0ESR0 CGU_ESR_FD0 Select spreading stage APB0_CLK APB1ESR0 CGU_ESR_FD0 Select spreading stage APB1_CLK APB2ESR0 CGU_ESR_FD0 Select spreading stage APB2_CLK APB3ESR0 CGU_ESR_FD0 Select spreading stage APB3_CLK MMIOESR0 CGU_ESR_FD0 Select spreading stage MMIO_HCLK AHB clock of Interrupt controller AHB0ESR CGU_ESR_FD0 Select sprea...

Page 81: ...r and the clock input pins 2 Fractional Divider Configuration registers If the application uses any of the Fractional Divider Configuration registers then the bits MADD and MSUB should be as large as possible in order to minimize power consumption 3 Power control registers The application initialization code should write all zeroes to each of the unnamed Power Control registers to minimize power c...

Page 82: ...address 0x8000 8020 A 0 in bit 1 Force CLKOUT of this register saves power by stopping CLKOUT when there are no SDRAM transactions and during self refresh mode 3 Static Memory Configuration registers A one in the bit 19 Write buffer Enable of the Static Memory Configuration registers enables the write buffers which reduces external memory traffic This improves memory bandwidth and reduces power co...

Page 83: ...trol register DADCCTRL 0x802003A8 A one in the bit 3 RPD of this register powers down the RADC A one in the bit 7 LPD powers down the LADC Dual channel 16 bit digital to analog converter Dual DAC Settings register DDACSET 0x802003A0 A zero in the bit 8 RDYNPON of this register powers down the right DAC A zero in the bit 9 LDYNPON powers down the left DAC SD MCI card interface 1 MCI Clock Enable re...

Page 84: ...memory features include Asynchronous page mode read Programmable wait states Bus turnaround delay Output enable and write enable delays Extended wait One chip select for synchronous memory and three chip selects for static memory devices Power saving modes dynamically control CKE and CLKOUT to SDRAMs Dynamic memory self refresh mode controlled by software Controller supports 2 k 4 k and 8 k row ad...

Page 85: ...nix HY57V283220 128 MB 4 M x 32 Samsung K4S560432 256 MB 64 M x 4 Samsung K4S560832 256 MB 32 M x 8 Samsung K4S561632E 256 MB 16 M x 16 Micron MT48LC64M4A2 256 MB 64 M x 4 Micron MT48LC32M8A2 256 MB 32 M x 8 Micron MT48LC16M16A2 256 MB 16 M x 16 Micron MT48LC8M32A2 256 MB 8 M x 32 Infineon HY39S256400 256 MB 64 M x 4 Infineon HY39S256800 256 MB 32 M x 8 Infineon HY39S256160 256 MB 16 M x 32 Hynix ...

Page 86: ...amples of page mode flash devices The EMC supports the 4 MB Intel 28F320J3 5 Implementation Operation notes To eliminate the possibility of endianness problems all data transfers to and from the registers of the EMC must be 32 bits wide Note If an register access is attempted with a size other than a word 32 bits it causes an ERROR response to the AHB bus and the transfer is terminated 5 1 Memory ...

Page 87: ...peration If the buffers are enabled an AHB write operation writes into the Least Recently Used LRU buffer if empty If the LRU buffer is not empty the contents of the buffer are flushed to memory to make space for the AHB write data If a buffer contains write data it is marked as dirty and its contents are written to memory before the buffer can be reallocated The write buffers are flushed whenever...

Page 88: ... are rejected and an error response is generated to the AHB bus Clearing the SREFREQ bit in the EMCDynamicControl Register returns the memory to normal operation See the memory data sheet for refresh requirements Note Static memory can be accessed normally when the SDRAM memory is in self refresh mode 6 1 Low power SDRAM Deep sleep mode The EMC supports JEDEC low power SDRAM deep sleep mode Deep s...

Page 89: ...tatic 2 MB DYCS 0x3000 0000 0x33FF FFFF and 0x5000 0000 0x53FF FFFF Dynamic 64 MB Table 76 Pad interface and control signal descriptions Name Type Value on POR reset Value during self refresh Description A 20 0 Output Low Depends on static memory accesses External memory address output Used for both static and SDRAM devices SDRAM memories only use A 14 0 D 15 0 Input Output Data outputs Low Depend...

Page 90: ...ry read strategy 0 R W 0x8000 8030 EMCDynamicRP Selects the precharge command period 0x0F R W 0x8000 8034 EMCDynamicRAS Selects the active to precharge command period 0xF R W 0x8000 8038 EMCDynamicSREX Selects the self refresh exit time 0xF R W 0x8000 803C EMCDynamicAPR Selects the last data out to active command time 0xF R W 0x8000 8040 EMCDynamicDAL Selects the data in to active command time 0xF...

Page 91: ...ct 1 to a read access 0x1F R W 0x8000 8230 EMCStaticWaitPage1 Selects the delay for asynchronous page mode sequential accesses for chip select 1 0x1F R W 0x8000 8234 EMCStaticWaitWr1 Selects the delay from chip select 1 to a write access 0x1F R W 0x8000 8238 EMCStaticWaitTurn1 Selects the number of bus turnaround cycles for chip select 1 0xF R W 0x8000 8240 EMCStaticConfig2 Selects the memory conf...

Page 92: ...bit to disable the EMC when the EMC is in idle state 1 Disabling the EMC reduces power consumption When the EMC is disabled the memory is not refreshed Write a 1 to this bit to re enable the EMC 1 1 Address Mirror This bit is set by power on reset When this bit is 1 accesses to the address ranges that would otherwise activate chip select 0 activate chip select 1 instead In applications that allow ...

Page 93: ...sets self refresh mode After a warm reset this bit reflects whether self refresh mode is in effect 1 1 Write Buffer Status This read only bit is 1 if write buffers are enabled and they contain data from a previous write operation Read this bit and if necessary wait for it to be 0 before setting low power or disabled mode in the EMCControl Register Power on reset clears this bit 0 2 Self Refresh Ac...

Page 94: ...c memory is placed in self refresh mode In self refresh mode data in dynamic memory will be preserved if the LPC288x is stopped or even powered down Write 0 to this bit to switch the EMC and dynamic memory to normal operating mode Write a 1 to this bit when the application is about to enter a low power mode in which it would not refresh dynamic memory The self refresh acknowledge bit in the EMCSta...

Page 95: ... of a reset cycle During this period HCLK runs at 12 MHz Therefore 12 MHz must be considered the clock rate for refresh calculations if refresh through warm reset is desired Note Refresh cycles are evenly distributed but there might be slight variations in the timing of refresh cycles depending on the status of the memory controller 13 DP Write a 1 to this bit to enter SDRAM deep power down mode S...

Page 96: ...028 Bit Symbol Value Description POR Reset Value 1 0 Read data strategy 00 Clock out delayed strategy using CLKOUT command not delayed clock out delayed POR reset value 00 01 Command delayed strategy using AHBHCLKDELAY command delayed clock out not delayed 10 Command delayed strategy plus one clock cycle using AHB HCLKDELAY command delayed clock out not delayed 11 Command delayed strategy plus two...

Page 97: ... is normally found in SDRAM data sheets as tSREX For devices without this parameter use the value of tXSR This register is accessed with one wait state Table 8 86 shows the EMCDynamictSREX Register Table 85 Dynamic Memory Active to Precharge Command Period Register EMCDynamictRAS address 0x8000 8034 Bit Symbol Description POR Reset Value 3 0 Active to precharge command period tRAS SDRAM initializa...

Page 98: ...abled mode This value is normally found in SDRAM data sheets as tDAL or tAPW This register is accessed with one wait state Table 8 88 shows the bit assignments for the EMCDynamicTDAL Register Table 87 Memory Last Data Out to Active Time Register EMCDynamictAPR address 0x8000 803C Bit Symbol Description POR Reset Value 3 0 Last data out to active command time tAPR SDRAM initialization code should w...

Page 99: ...EMCDynamictRC Register 10 14 Dynamic Memory Auto refresh Period Register EMCDynamictRFC 0x8000 804C The EMCDynamicTRFC Register controls the auto refresh period and auto refresh to active command period tRFC This register should only be modified during system initialization or when there are no current or outstanding transactions This can be Table 89 Dynamic Memory Write recover Time Register EMCD...

Page 100: ...ere are no current or outstanding transactions This can be ensured by waiting until the EMC is idle and then entering low power or disabled mode This value is normally found in SDRAM data sheets as tRRD This register is accessed with one wait state Table 8 93 shows the EMCDynamictRRD Register Table 91 Dynamic Memory Auto refresh Period Register EMCDynamictRFC address 0x8000 804C Bit Symbol Descrip...

Page 101: ...essed with one wait state Table 8 95 shows the EMCDynamicConfig Register Table 93 Dynamic Memory Active Bank A to Active Bank B Time Register EMCDynamictRRD address 0x8000 8054 Bit Symbol Description POR Reset Value 3 0 Active bank A to active bank B latency tRRD SDRAM initialization code should write this field with one less than the number of AHB HCLK cycles that equals or just exceeds the tRRD ...

Page 102: ...See Table 8 96 2 000000 13 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 14 Address Mapping Address mapping control See Table 8 96 0 18 15 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 19 Buffer Enable When this bit is 1 the read and write buffers are enabled for acce...

Page 103: ...32Mx16 4 banks row length 13 col length 10 23 11 25 13 25 11 16 bit external bus low power SDRAM address mapping Bank Row Column 0 1 000 00 2Mx8 2 banks row length 11 col length 9 20 10 21 11 21 0 1 000 01 1Mx16 2 banks row length 11 col length 8 19 9 20 10 9 0 1 001 00 8Mx8 4 banks row length 12 col length 9 21 10 23 12 23 11 0 1 001 01 4Mx16 4 banks row length 12 col length 8 20 9 22 11 21 9 0 1...

Page 104: ...erved bit is not defined Table 97 Dynamic Memory RAS CAS Delay Register EMCDynamicRasCas 0x8000 8104 Bit Symbol Description POR Reset Value Table 98 Static Memory Configuration Registers EMCStaticConfig0 2 addresses 0x8000 8200 0x8000 8220 0x8000 8240 Bit Symbol Description POR Reset Value 1 0 Memory Width This field selects the width of the associated memory Do not write the values 10 or 11 00 8 ...

Page 105: ... to their UBn and LBn upper byte and lower byte inputs In this case for reads both UBn and LBn should be asserted low so that the memory drives both lanes of the bus Regardless of this bit for write operations one or both of BLSn 1 0 go low to indicate which byte s should be written 0 8 Extended Wait If this bit is zero as it is after a power on reset the EMCStaticWaitRd and EMCStaticWaitWr Regist...

Page 106: ...ions This can be ensured by waiting until the EMC is idle and then entering low power or disabled mode This register is not used if the Extended Wait bit in the EMCStaticConfig0 2Register is 1 These registers are accessed with one wait state Table 8 101 shows the EMCStaticWaitRd0 2 Registers Table 99 Static Memory Write Enable Delay registers EMCStaticWaitWen0 2 addresses 0x8000 8204 0x8000 8224 0...

Page 107: ...ry Read Delay Registers EMCStaticWaitRd0 2 addresses 0x8000 820C 0x8000 822C 0x8000 824C Bit Symbol Description Reset Value 4 0 WAITRD Static memory initialization code should write this field with one less than the number of AHB HCLK cycles that equals or just exceeds the LPC288x max for clock to chip select assertion plus the SDRAM max access time from chip select plus the LPC288x min read data ...

Page 108: ...dified during system initialization or when there are no current or outstanding transactions However if necessary these control bits can be altered during normal operation This register is accessed with one wait state Table 8 105 shows the EMCStaticExtendedWait Register Table 103 Static Memory Write Delay Registers 0 2 EMCStaticWaitWr0 2 addresses 0x8000 8214 0x8000 8234 0x8000 8254 Bit Symbol Des...

Page 109: ...nes to reserved bits The value read from a reserved bit is not defined 16 10 6 50 10 6 16 1 49 Table 106 EMC Miscellaneous Control Register EMCMisc address 0x8000 5064 Bit Symbol Description Reset Value 0 SRefReq This bit is an alternative method of placing external SDRAM in self refresh mode the other being bit 2 in the EMCDynamicControl register A 1 in this bit places the SDRAM in self refresh m...

Page 110: ... Table 8 96 10 Write 0x083 to the EMCDynamicControl Register This changes the command to the SDRAM s to MODE which allows programming the Mode register in the SDRAM 11 The Mode register s in the SDRAM s is are programmed by reading a particular address in the SDRAM address range Consult the SDRAM data sheet for the format of its Mode register Since the LPC288x uses a 16 bit wide data bus for SDRAM...

Page 111: ...l efficiency The SDRAM is now ready for normal operation 12 SDRAM usage notes This section uses the Micron MT48LC8M16A2 module 8 M 16 bit as an example of how to program the MODE register in this SDRAM module The Micron MT48LC8M16A2 module has 4 K rows and 512 columns The address mapping is shown in Table 8 108 For other address mapping configurations see also Section 8 12 1 1 and Section 8 12 1 2...

Page 112: ...d settings According to these settings the MODE register should be programmed with the value 100011b Table 109 Micron MT48LC8M16A2 MODE register Address bus MODE register bit MODE register description Value Value programmed in example A0 A1 A2 2 0 Burst Length 0 0 0 A3 0 and A3 1 burst length 1 0 0 1 A3 0 and A3 1 burst length 2 0 1 0 A3 0 and A3 1 burst length 4 0 1 1 A3 0 and A3 1 burst length 8...

Page 113: ...ress and BAn is the bank address 12 1 1 32 bit memory data bus width Table 110 Address mapping control bits in EMCDynamicConfig for Micron MT48LC8M16A2 14 12 11 9 8 7 Description Row addr bits BA1 bit 16 bit external bus low power SDRAM address mapping Bank Row Column 0 1 010 01 8Mx16 4 banks row length 12 col length 9 21 10 23 Table 111 32 bit memory bus width SDRAM address mapping 2 K rows 256 5...

Page 114: ...0 C5 C4 C3 C2 C1 C0 B1 B0 C5 C4 C3 C2 C1 C0 B1 B0 C5 C4 C3 C2 C1 C0 B1 B0 Table 113 32 bit memory bus width SDRAM address mapping 8 K rows 256 512 1025 2048 columns A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 BA1 BA0 R12 R11 R10 R9 R8 BA1 BA0 R12 R11 R10 R9 R8 R7 BA1 BA0 R12 R11 R10 R9 R8 R7 R6 BA1 BA0 R12 R11 R10 R9 R8 R7 R6 R5 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 R7 R6 R5 R4 R3 R2 R1 R0 C7 C6 R6 R5...

Page 115: ...10 R9 BA1 BA0 R11 R10 R9 R8 BA1 BA0 R11 R10 R9 R8 R7 BA1 BA0 R11 R10 R9 R8 R7 R6 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 R8 R7 R6 R5 R4 R3 R2 R1 R0 C7 R7 R6 R5 R4 R3 R2 R1 R0 C8 C7 R6 R5 R4 R3 R2 R1 R0 C9 C8 C7 R5 R4 R3 R2 R1 R0 C10 C9 C8 C7 A7 A6 A5 A4 A3 A2 A1 A0 C6 C5 C4 C3 C2 C1 C0 B0 C6 C5 C4 C3 C2 C1 C0 B0 C6 C5 C4 C3 C2 C1 C0 B0 C6 C5 C4 C3 C2 C1 C0 B0 Table 116 16 bit memory bus width SDRAM ...

Page 116: ... rights reserved User manual Rev 02 1 June 2007 116 of 362 NXP Semiconductors UM10208 Chapter 8 LPC2800 EMC A7 A6 A5 A4 A3 A2 A1 A0 C6 C5 C4 C3 C2 C1 C0 B0 C6 C5 C4 C3 C2 C1 C0 B0 C6 C5 C4 C3 C2 C1 C0 B0 C6 C5 C4 C3 C2 C1 C0 B0 ...

Page 117: ...the device If more than one request is assigned to the FIQ class the FIQ service routine can read a word from the interrupt controller that identifies which FIQ source s is are requesting an interrupt 3 Interrupt sources Table 9 117 lists the interrupt sources for each peripheral function and the bit number s or register number s associated with each Each peripheral device may have one or more int...

Page 118: ...9 3 1 11 MCI interrupt 2 from Secure Digital and Multimedia Card Interface see Section 9 3 1 12 UART Receiver Error Flag 13 I2C Transmit Done 14 reserved 15 reserved 16 SAI1 17 reserved 18 reserved 19 SAI4 20 SAO1 21 SAO2 22 reserved 23 Flash 24 LCD Interface 25 GPDMA 26 USB 2 0 High Speed Device interface low priority interrupt see Section 9 3 1 27 USB 2 0 High Speed Device interface high priorit...

Page 119: ...t controller input 10 while MCI interrupt 2 is connected to interrupt controller input 11 Two interrupt priorities may be selected for the USB function interrupts not the USB DMA interrupts via the USB Interrupt Priority Register USBIntP Interrupts configured as low priority are connected to interrupt controller input 26 and interrupts configured as high priority are connected to interrupt control...

Page 120: ...s The IRQ service routine should read this register which also yields the bit register number of the interrupting source in bits 7 3 This address can then be used to access the address of the individual service routine and the priority limit value to write into INT_PRIOMASK0 R W X 0x8030 0100 INT_VECTOR1 Vector 1 Bits 31 11 are R W If more than one interrupt source is mapped to FIQ these bits shou...

Page 121: ... 0 17 ACTVLO Since all interrupt sources on the LPC288x are active high there is no reason to write a 1 to this bit 0 24 18 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 25 WE_ACTVLO Since all interrupt sources on the LPC288x are active high there is no reason to write a 1 to this bit NA 26 WE_ENABLE If a 1 is written to this WO bit...

Page 122: ...bit register number of the source that caused the interrupt Zero in this field indicates that no interrupt with priority above the current priority threshold is pending The ISR can then use the 32 bit value to access the address of the specific interrupt service routine for this source from the first word of the table entry and a value to program into the corresponding INT_PRIOMASK register from t...

Page 123: ...he processor 2 The processor latches the IRQ state Table 122 Priority Mask Registers INT_PRIOMASK0 1 0x8030 0000 0x8030 0004 Bits Name Description Reset value 3 0 Priority Limit INT_PRIOMASK0 applies to IRQ ISRs INT_PRIOMASK1 to FIQ ISRs This register defines the current interrupt priority and allows nested interrupt service If an ISR is going to allow nested interrupts it should 1 read this regis...

Page 124: ...ts the ARM7 family will still take the interrupt This occurs for both IRQ and FIQ interrupts For example consider the following instruction sequence MRS r0 cpsr ORR r0 r0 I_Bit OR F_Bit disable IRQ and FIQ interrupts MSR cpsr_c r0 If an IRQ interrupt is received during execution of the MSR instruction then the behavior will be as follows The IRQ interrupt is latched The MSR cpsr r0 executes to com...

Page 125: ...st not be disabled for more than a few cycles 6 2 Workaround There are 3 suggested workarounds Which of these is most applicable will depend upon the requirements of the particular system 6 2 1 Solution 1 Test for an IRQ received during a write to disable IRQs Add code similar to the following at the start of the interrupt routine SUB lr lr 4 Adjust LR to point to return STMFD sp lr Get some free ...

Page 126: ...l ROM or RAM is read when the reset sequence begins at address 0 following a warm reset This bit power on resets to 0 so that POR is always from internal ROM Although multiple sources can be selected to generate FIQ requests there is one starting point for all FIQ interrupts Therefore if more than one interrupt sources are classified as FIQ the FIQ interrupt service routine must read INT_VECTOR1 t...

Page 127: ...means like reading data from the device writing data to the device or simply disabling the device from requesting further interrupts Finally the interrupt service routine needs to restore processor registers and context and return to the interrupted process A non nested ISR also needs to re enable interrupts while a nested routine needs to restore the value of the INT_PRIOMASK 0 or 1 register that...

Page 128: ...t their interrupt requests when they count down to zero If interrupt is not desired the request s can be disabled in the interrupt controller 3 Register descriptions 3 1 Timer register map UM10208 Chapter 10 Timer Rev 02 1 June 2007 User manual Table 124 Timer registers Names Description Access Reset value Addresses T0LOAD T1LOAD Load Registers Writing to this address immediately loads both the ma...

Page 129: ...d not write ones to reserved bits The value read from a reserved bit is not defined 3 2 PRESCALE This field controls how the CGU clock is prescaled before being applied to the main counter 00 decrement main counter at CGU clock rate 01 decrement main counter at CGU clock rate 16 10 decrement main counter at CGU clock rate 256 11 do not write undef 5 4 Reserved user software should not write ones t...

Page 130: ... WDT clock edge the Prescale Counter is cleared and the 32 bit Timer Counter is incremented Thus the Prescale facility divides the WDT clock by the value in the Prescale Register plus one The value of the Timer Counter is continually compared to the values in two registers called Match Register 0 and 1 When if the value of the Timer Counter matches that of Match Register 0 at a WDT clock edge a si...

Page 131: ...lue in this register plus one for incrementing the Timer Counter R W 0 0x8000 280C WDT_MCR Match Control Register Controls what happens when the Timer Counter matches the Match Registers R W 0 0x8000 2814 WDT_MR0 Match Register 0 An interrupt can be arranged when the Timer Counter matches the value in this register R W 0 0x8000 2818 WDT_MR1 Match Register 1 The LPC288x can be reset if the Timer Co...

Page 132: ...hdog Timer Control Register WDT_TCR 0x8000 2804 Bit Function Description Reset value 0 Counter Enable When this bit is 1 the Prescale Counter and Timer Counter are enabled to count in response to WDT clocks from the CGU When it is 0 both counters are disabled 0 1 Counter Reset When this bit is 1 the Prescale Counter and Timer Counter are cleared at the next WDT clock edge from the CGU Write a 1 to...

Page 133: ...ch When this bit is 1 bit 0 Counter Enable in the WDT_TCR is cleared when the TC matches MR0 so that further counting is disabled For Watchdog applications leave this bit 0 so that the TC can continue on to the MR1 Reset value 0 3 Enable MR1 Status If this bit is 1 bit 1 of the WDT_SR is set when the Timer Counter matches MR1 If this event causes the LPC288x to be reset there is no reason to set t...

Page 134: ...d not write ones to reserved bits The value read from a reserved bit is not defined 5 4 Enable Interrupt This field controls how a match between TC and MR0 affects the m0 output that is sent to the Event Router 0x disable the Watchdog Interrupt function 10 enable the Watchdog Interrupt function 11 do not use 00 6 Reserved user software should not write ones to reserved bits The value read from a r...

Page 135: ...Group 2 Set an Interrupt Output Mask bit so that Event Router interrupt output 0 will be asserted if m0 goes high Int Controller INT_REQ1 0x1401 000x Per Table 9 117 on page 117 Event Router interrupt output 0 is bit register number 1 so it s controlled by INT_REQ1 Enable Event Router output 0 to interrupt at priority level x x 0 WDT WDT_TCR 0x0001 Enable WDT operation Table 138 Sample setup Modul...

Page 136: ...ity and sensitivity logic can be read from Raw Status Registers 0 3 Each active state is next masked enabled by a global mask bit for that signal The results can be read from Pending Registers 0 3 All 99 Pending signals are presented to each of the five output logic blocks Each output logic block includes a set of four Interrupt Output Mask Registers each set totalling 99 bits that control whether...

Page 137: ... UVBUS P7 0 3 9 D8 P0 8 0 10 DYCS P1 8 1 10 MCMD P5 1 2 10 USBbusres 2 3 10 D9 P0 9 0 11 CKE P1 9 1 11 MD3 P5 2 1 2 11 reserved 3 11 D10 P0 10 0 12 DQM0 P1 10 1 12 MD2 P5 3 1 2 12 3 12 D11 P0 11 0 13 DQM1 P1 11 1 13 MD1 P5 4 1 2 13 3 13 D12 P0 12 0 14 BLS0 P1 12 1 14 MD0 P5 5 1 2 14 3 14 D13 P0 13 0 15 BLS1 P1 13 1 15 RXD P6 0 1 2 15 3 15 D14 P0 14 0 16 MCLKO P1 14 1 16 TXD P6 1 2 16 3 16 D15 P0 1...

Page 138: ...ave no effect These registers can be used to force an interrupt or wakeup WO 0x8000 0C40 0x8000 0C44 0x8000 0C48 0x8000 0C4C EVRSR 0 EVRSR 1 EVRSR 2 EVRSR 3 Raw Status Registers Each 1 in these read only registers indicates that the corresponding signal is in its active state or that an the edge selected by the corresponding bit in EVAPR has been detected R W 0x8000 0D20 0x0003 FBFC 0x8000 0D24 0x...

Page 139: ... 0x8000 1880 0x8000 1884 0x8000 1888 0x8000 188C EVIOMS 0 4 0 3 Interrupt Output Mask Set Registers The first digit in the names of these 20 registers indicates which output signal the register applies to the second digit indicates which group of input signals the register applies to Writing 1s to these registers set the corresponding bits of the Interrupt Output Mask Registers thus enabling the c...

Page 140: ...1420 0x8000 1440 0x8000 1460 0x8000 1480 EVIOMC 0 4 0 0x8000 1800 0x8000 1820 0x8000 1840 0x8000 1860 0x8000 1880 EVIOMS 0 4 0 0x8000 1C00 0x8000 1C20 0x8000 1C40 0x8000 1C60 0x8000 1C80 EVIOP 0 4 0 0x8000 1000 0x8000 1020 0x8000 1040 0x8000 1060 0x8000 1080 Table 142 Bit Signal correspondence in input group 0 registers Bit 31 30 29 28 27 26 25 24 Signal A13 P0 29 A12 P0 28 A11 P0 27 A10 P0 26 A9 ...

Page 141: ...44 0x8000 1464 0x8000 1484 EVIOMC 0 4 1 0x8000 1804 0x8000 1824 0x8000 1844 0x8000 1864 0x8000 1884 EVIOMS 0 4 1 0x8000 1C04 0x8000 1C24 0x8000 1C44 0x8000 1C64 0x8000 1C84 EVIOP 0 4 1 0x8000 1004 0x8000 1024 0x8000 1044 0x8000 1064 0x8000 1084 Table 144 Bit Signal correspondence in input group 1 registers Bit 31 30 29 28 27 26 25 24 Signal LER P4 3 LRW P4 2 LRS P4 1 LCS P4 0 DATO P3 6 BCKO P3 5 W...

Page 142: ...00 1408 0x8000 1428 0x8000 1448 0x8000 1468 0x8000 1488 EVIOMC 0 4 2 0x8000 1808 0x8000 1828 0x8000 1848 0x8000 1868 0x8000 1888 EVIOMS 0 4 2 0x8000 1C08 0x8000 1C28 0x8000 1C48 0x8000 1C68 0x8000 1C88 EVIOP 0 4 2 0x8000 1008 0x8000 1028 0x8000 1048 0x8000 1068 0x8000 1088 Table 146 Bit Signal correspondence in input group 2 registers Bit 31 30 29 28 27 26 25 24 Signal SCL RXD P6 0 1 WDOG MD3 P5 2...

Page 143: ...C EVIOMC 0 4 3 0x8000 180C 0x8000 182C 0x8000 184C 0x8000 186C 0x8000 188C EVIOMS 0 4 3 0x8000 1C0C 0x8000 1C2C 0x8000 1C4C 0x8000 1C6C 0x8000 1C8C EVIOP 0 4 3 0x8000 100C 0x8000 102C 0x8000 104C 0x8000 106C 0x8000 108C Table 148 Bit Signal correspondence in input group 3 registers Bit 31 30 29 28 27 26 25 24 Signal reserved Bit 23 22 21 20 19 18 17 16 Signal reserved Bit 15 14 13 12 11 10 9 8 Sig...

Page 144: ...ead only register allows general purpose software to determine how many inputs and outputs the Event Router includes Table 150 Features Register EVFEATURES 0x8000 0E00 Bits Symbol Description Reset Value 7 0 n The number of inputs included in the Event Router minus 1 106 21 16 m The number of outputs produced by the Event Router minus 1 4 31 22 Reserved The value read from a reserved bit is not de...

Page 145: ...for measuring time when system power is on and optionally when it is off It uses little power in either mode 3 Architecture 4 RTC usage notes On the LPC288x the clock for the RTC is created by the Clock Generation Unit CGU The PWR_UP signal shown in the preceding Figure enables use of the RTC and is controlled by the RTC Configuration Register as described in Section 13 6 1 1 5 RTC interrupts Inte...

Page 146: ...e 151 Real Time Clock register map Name Size Description Access Reset Value 1 Address RTC_CFG 1 RTC Configuration Register R W 0 0x8000 5024 ILR 2 Interrupt Location Register R W 0x8000 2000 CTC 15 Clock Tick Counter RO 0x8000 2004 CCR 4 Clock Control Register R W 0x8000 2008 CIIR 8 Counter Increment Interrupt Register R W 0x8000 200C AMR 8 Alarm Mask Register R W 0x8000 2010 CTIME0 32 Consolidate...

Page 147: ...the interrupt that is detected by the read Table 152 Miscellaneous registers Name Size Description Access Address RTC_CFG 1 Enables or disables software access to the RTC R W 0x8000 5024 ILR 3 Interrupt Location Reading this location indicates the source of an interrupt Writing a one to the appropriate bit at this location clears the associated interrupt R W 0x8000 2000 CTC 15 Clock Tick Counter V...

Page 148: ...t location clears the alarm interrupt NC 31 2 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 155 Clock Tick Counter Register CTCR address 0x8000 2004 Bit Symbol Description Reset value 14 0 Clock Tick Counter Prior to the Seconds counter the CTC counts 32 768 clocks per second NA 31 15 Reserved user software should not write...

Page 149: ... read only To write new values to the Time Counters the Time Counter addresses should be used 3 IMDOM When 1 an increment of the Day of Month value generates an interrupt NA 4 IMDOW When 1 an increment of the Day of Week value generates an interrupt NA 5 IMDOY When 1 an increment of the Day of Year value generates an interrupt NA 6 IMMON When 1 an increment of the Month value generates an interrup...

Page 150: ...rved bit is not defined NA 20 16 Hours Hours value in the range of 0 to 23 NA 23 21 Reserved The value read from a reserved bit is not defined NA 26 24 Day Of Week Day of week value in the range of 0 to 6 NA 31 27 Reserved The value read from a reserved bit is not defined NA Table 160 Consolidated Time register 1 CTIME1 address 0x8000 2018 Bit Symbol Description Reset value 4 0 Day of Month Day of...

Page 151: ... compared with the time counters If all the unmasked See Section 13 6 1 6 Alarm Mask Register AMR 0x8000 2010 on page 149 alarm registers match their corresponding time counters then an interrupt is generated The interrupt is cleared when a one is written to bit one of the Interrupt Location Register ILR 1 Table 162 Time Counter relationships and values Counter Size Enabled by Minimum value Maximu...

Page 152: ...ss ALSEC 6 Alarm value for Seconds R W 0x8000 2060 ALMIN 6 Alarm value for Minutes R W 0x8000 2064 ALHOUR 5 Alarm value for Hours R W 0x8000 2068 ALDOM 5 Alarm value for Day of Month R W 0x8000 206C ALDOW 3 Alarm value for Day of Week R W 0x8000 2070 ALDOY 9 Alarm value for Day of Year R W 0x8000 2074 ALMON 4 Alarm value for Months R W 0x8000 2078 ALYEAR 12 Alarm value for Years R W 0x8000 207C ...

Page 153: ...sor Latch Access Bit DLAB LCR bit 7 enables access to the Divisor Latches UM10208 Chapter 14 Universal Asynchronous Receiver Transmitter UART Rev 02 1 June 2007 User manual Table 165 UART Pin Description Pin Type Description RXD Input Serial Input Serial receive data TXD Output Serial Output Serial transmit data RTS Output Receive Flow Control CTS Input Transmit Flow Control Table 166 UART Registe...

Page 154: ...Register R W 0x00 0x8010 101C ACR Auto baudControl Register R W 0x00 0x8010 1020 ICR IrDA Control Register R W 0 0x8010 1024 FDR Fractional Divider Register R W 0x10 0x8010 1028 POP NHP Pop Register WO 0 0x8010 1030 MODE NHP Mode Selection R W 0 0x8010 1034 INTCE Interrupt Clear Enable Register WO 0 0x8010 1FD8 INTSE Interrupt Set Enable Register WO 0 0x8010 1FDC INTS Interrupt Status Register RO ...

Page 155: ...or Latch LSB Register DLL 0x8010 1000 when DLAB 1 3 4 Divisor Latch MSB Register DLM 0x8010 1004 when DLAB 1 The Divisor Latch is part of the Baud Rate Generator and holds the value used to divide the UART baud rate clock UART_CLK in order to produce the baud rate clock which must be 16x the desired baud rate The DLL and DLM registers together form a 16 bit divisor where DLL contains the lower 8 b...

Page 156: ...rupt Enable Register IER 0x8010 1004 when DLAB 0 Bit Name Description Reset Value 0 RDAIntEn A 1 in this bit enables the Receive Data Available interrupt It also controls the Character Receive Time out interrupt 0 1 THREIntEn A 1 in this bit enables the THRE interrupt THRE can be read as LSR 5 0 2 RLSIntEn A 1 in this bit enables RX line status interrupts The status of this interrupt can be read f...

Page 157: ...a block of data defined by the trigger level The CTI interrupt IIR 3 1 110 is a second level interrupt and is set when the Rx FIFO contains at least one character and no Rx FIFO activity has occurred in 3 5 to 4 5 character times Any Rx FIFO activity read or write of the RSR will clear the interrupt This interrupt is intended to flush the RBR after a message has been received that is not a multipl...

Page 158: ...time since the last THRE 1 event This delay is provided to give the CPU time to write data to the THR without a THRE interrupt to decode and service A THRE interrupt is set immediately if the THR FIFO has held two or more characters at one time and currently the THR is empty The THRE interrupt is reset when the THR is written or IIR is read and THRE is the highest interrupt IIR 3 1 001 Table 173 I...

Page 159: ...O Reset 0 No impact on either FIFO 0 1 Writing a 1 to FCR 2 clears all bytes in the Tx FIFO and resets the pointer logic This bit always reads as 0 3 DMAMode If the FIFO Enable FCR0 is 1 and the SDMA facility is used to transfer data to or from the UART this bit controls when DMA transfers are requested 0 0 Rx DMA is requested when the Rx FIFO is not empty Tx DMA is requested when the Tx FIFO is e...

Page 160: ...LCR 1 0 00 3 Parity Enable 0 Disable parity generation and checking 0 1 Enable parity generation and checking 5 4 Parity Select 00 Odd parity The number of 1s in each transmitted character and the attached parity bit will be odd 0 01 Even Parity The number of 1s in each transmitted character and the attached parity bit will be even 10 Send 1 in parity bits 11 Send 0 in parity bits 6 Break Control ...

Page 161: ... software should not write ones to reserved bits The value read from a reserved bit is not defined 1 RTS If the autoRTS bit MCR6 is 1 this bit is read only and reflects the current state of the RTS pin If autoRTS is 0 this bit controls the RTS pin In either case a 1 in this bit is equivalent to RTS low a 0 to RTS high This bit reads as 0 when modem loopback mode is active 0 3 2 Reserved user softw...

Page 162: ...ter from sending CTS must go high before the middle of the transmitted stop bit In Auto CTS mode a change of CTS does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set However the Delta CTS bit in the MSR will be set Table 14 177 lists the conditions for generating a Modem Status interrupt The auto CTS function reduces interrupts on the LPC288x When flow control is en...

Page 163: ...SR clears this bit 0 2 Parity Error PE This bit is 1 if LCR3 is 1 and the parity bit of the character at the top of the Rx FIFO does not match the checking criterion in LCR5 4 Reading the LSR clears this bit This bit is significant only when RDR LSR0 is 1 0 3 Framing Error FE This bit is 1 if the UART sampled the RXD signal low at the center of the stop bit of the character at the top of the Rx FI...

Page 164: ...R This bit is cleared when the LSR is read and there are no subsequent errors in the RxFIFO 0 31 8 Reserved The value read from a reserved bit is not defined Table 178 Line Status Register LSR 0x8010 1014 read only Bit Name Description Reset Value Table 179 Modem Status Register MSR 0x8010 1018 read only Bit Name Description Reset Value 0 DTCS Delta Clear to Send This bit is set when the CTS pin c...

Page 165: ...can be used to automatically restart baud rate measurement if a time out occurs the rate measurement counter overflows If this bit is set the rate measurement will restart at the next falling edge of the RXD pin The auto baud function can generate two interrupts The IIR ABTOInt interrupt will get set if the interrupt is enabled IER ABToIntEn is set and the auto baud rate measurement counter overfl...

Page 166: ... delimited by two falling edges When the ACR_Start bit is set the auto baud protocol will execute the following phases 1 On ACR_Start bit setting the baud rate measurement counter is reset and the RSR is reset The RSR baud rate is switched to the highest rate 2 A falling edge on RXD triggers the beginning of the start bit The rate measuring counter will start counting UART_CLK cycles optionally pr...

Page 167: ...nly start bit is used for autobaud Fig 23 Autobaud a mode 0 and b mode 1 waveform UART RX start bit LSB of A or a ACR start rate counter start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop A 0x41 or a 0x61 16 cycles 16 cycles 16xbaud_rate UARTn RX start bit LSB of A or a rate counter A 0x41 or a 0x61 start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop ACR start 16 cycles 16xbaud_rate ...

Page 168: ...1 in this bit inverts the serial input This has no effect on the serial output 0 2 FixPulseEn A 1 in this bit selects IrDA fixed pulse width mode 0 5 3 PulseDiv Configures the pulse when FixPulseEn 1 See text below for details 0 31 6 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 183 IrDA pulse width FixPulseEn PulseDiv IrDA tr...

Page 169: ...GU The value of the FDR should not be modified while transmitting receiving data or data may be lost or corrupted Usage Note For practical purposes the UART baud rate formula can be written in a way that identifies the part of a baud rate generated without the fractional baud rate generator and the correction factor that this module adds 4 Based on this representation fractional baud rate generato...

Page 170: ...3 hex 2 dec 1 50 61A8 25000 0 0000 25000 1 1 0 0 0000 75 411B 16667 0 0020 12500 3 3 1 0 0000 110 2C64 11364 0 0032 6250 11 11 9 0 0000 134 5 244E 9294 0 0034 3983 3 3 4 0 0001 150 208D 8333 0 0040 6250 3 3 1 0 0000 300 1047 4167 0 0080 3125 3 3 1 0 0000 600 0823 2083 0 0160 1250 3 3 2 0 0000 1200 0412 1042 0 0320 625 3 3 2 0 0000 1800 02B6 694 0 0640 625 9 9 1 0 0000 2000 0271 625 0 0000 625 1 1 ...

Page 171: ...its The value of reserved bits when read is not defined 1 Table 187 NHP Pop Register POP 0x8010 1030 Bit Name Description Reset value When bit 0 of the NHP Mode Register is 1 writing to this write only register removes the byte from the RBR and Rx FIFO In NHP mode this register should be written after reading a byte from the RBR because doing so does not remove the byte from the RBR Table 188 Inte...

Page 172: ... set when parity checking is enabled in the LCR and the character in the RBR had a Parity Error It is cleared by popping the RBR 0 15 OEInt This bit is set when the RBR and Rx FIFO if enabled overruns so that a character is lost It is cleared by writing a 1 to bit 15 of the INTCS register 0 31 16 Reserved The value of reserved bits when read is not defined Table 188 Interrupt Status Register INTS ...

Page 173: ...it sets the ABEOInt bit in the INTS register 9 ABTOIntSet Writing a 1 to this bit sets the ABTOInt bit in the INTS register 14 10 Reserved Software should not write ones to reserved bits 15 OEIntSet Writing a 1 to this bit sets the OEInt bit in the INTS register 31 16 Reserved Software should not write ones to reserved bits Table 191 Interrupt Set Enable Register INTSE 0x8010 1FDC Bit Name Descrip...

Page 174: ...n the INTE register 11 10 Reserved Software should not write ones to reserved bits 12 BreakIEClr Writing a 1 to this clears the BreakIE bit in the INTE register 13 FEIEClr Writing a 1 to this clears the FEIE bit in the INTE register 14 PEIEClr Writing a 1 to this clears the PEIE bit in the INTE register 15 OEIEClr Writing a 1 to this bit clears the OEIE bit in the INTE register 31 16 Reserved Soft...

Page 175: ...a written to the TX Holding Register FIFO THR in the Tx FIFO The TX Shift Register TSR takes characters from the Tx FIFO and serializes them onto the serial output pin TXD The Baud Rate Generator block BRG generates the clock used by the RX and TX blocks The BRG clock input source is the CGU and the clock is divided by the divisor in the DLL and DLM registers This divided clock must be 16 times th...

Page 176: ...v 02 1 June 2007 176 of 362 NXP Semiconductors UM10208 Chapter 14 LPC2800 UART Fig 24 UART block diagram APB INTERFACE LCR RECEIVER LSR FCR BRG TRANSMITTER INTERRUPT UART interrupt SCR TXD NBAUDOUT RXD RBR RSR DLM DLL THR TSR IIR IER MODEM RTS MCR MSR CTS FDR ...

Page 177: ...supported by ARM DMA channels specifically single but not burst operation Memory to memory memory to peripheral peripheral to memory and peripheral to peripheral transfers Scatter or gather DMA is supported through the use of linked lists This means that successive source or destination areas do not have to occupy contiguous areas of memory Rotating channel priority Each DMA channel has equal oppo...

Page 178: ...nd written using word 32 bit operations 3 1 2 Bus and transfer widths The physical width of the AHB bus is 32 bits Source and destination transfers must be of the same width 8 16 or 32 bits 3 1 3 Endian behavior GPDMA channels can swap bytes between a big endian source and a little endian destination or between a little endian source and a big endian destination 3 1 4 Error conditions A peripheral...

Page 179: ...hannel s Source or Destination Address Register 2 The channel s Configuration register must be programmed to respond to the peripheral s request signal Table 15 194 shows the values to be programmed into the Configuration register for each of the supported peripherals The final two entries in the table above represent external requests for DMA transfer If only one such request is needed connecting...

Page 180: ...channel enabled MPMC_A20 3 MPMC_A18 5 Table 196 GPDMA register map Name Description Access Reset value Address Channel Registers DMA0Source Channel 0 Source Address Register R W 0 0x8010 3800 DMA0Dest Channel 0 Destination Address Register R W 0 0x8010 3804 DMA0Length Channel 0 Transfer Length Register R W 0x0FFF 0x8010 3808 DMA0Config Channel 0 Configuration Register R W 0 0x8010 380C DMA0Enab Ch...

Page 181: ...DMA5AltSource DMA5AltConfig Channel 5 Alternate Registers as described for Channel 0 WO 0x8010 3A50 0x8010 3A5C DMA6AltSource DMA6AltConfig Channel 6 Alternate Registers as described for Channel 0 WO 0x8010 3A60 0x8010 3A6C DMA7AltSource DMA7AltConfig Channel 7 Alternate Registers as described for Channel 0 WO 0x8010 3A70 0x8010 3A7C Global Registers DMA_Enable Global Enable Register R W 0 0x8010 ...

Page 182: ...nts of this register are NOT incremented during the transfer 0 Table 199 Transfer Length Register DMA 0 7 Length 0x8010 3808 38E8 Bit Symbol Description Reset Value 11 0 The maximum number of transfers to be performed minus one The maximum number of transfers without software attention is 4096 This can represent 4096 8192 or 16384 bytes depending on whether the channel s Configuration register def...

Page 183: ...pEndian If this bit is 1 and the Size field is 0x the GPDMA channel swaps data between Big and LIttle Endian formats for each read and write operation For Size 32 bits it exchanges the MS and LS bytes as well as the two middle bytes of each word For Size 16 bits it exchanges the two bytes in each halfword A GPDMA channel can be used to change the endian ness of data in place in a memory buffer by ...

Page 184: ...MA_IRQStat and clears this register when bits 11 0 of this register match bits 11 0 of its Transfer Length Register Reading this register while a transfer is in progress returns the current count value Write any value to this register to clear it to 0 Software firmware needs to do this if it disabled a channel while a buffer was in progress or if a source peripheral terminated a buffer prematurely...

Page 185: ... Length Register NA 31 12 Reserved user software should not write ones to reserved bits Table 206 Alternate Configuration Registers DMA 0 7 AltConfig 0x8010 3A0C 3A7C Bit Symbol Description Reset Value 18 0 This write only register can be used to set a channel s configuration just like the main Channel Configuration Register NA 31 19 Reserved user software should not write ones to reserved bits Ta...

Page 186: ...dicates that channel 1 has half finished a buffer 0 4 Complete2 A 1 in this bit indicates that channel 2 has finished a buffer 0 5 Half2 A 1 in this bit indicates that channel 2 has half finished a buffer 0 6 Complete3 A 1 in this bit indicates that channel 3 has finished a buffer 0 7 Half3 A 1 in this bit indicates that channel 3 has half finished a buffer 0 8 Complete4 A 1 in this bit indicates ...

Page 187: ...en channel 3 has finished a buffer 1 7 MaskHalf3 A 1 in this bit prevents an interrupt when channel 3 has half finished a buffer 1 8 MaskComp4 A 1 in this bit prevents an interrupt when channel 4 has finished a buffer 1 9 MaskHalf4 A 1 in this bit prevents an interrupt when channel 4 has half finished a buffer 1 10 MaskComp5 A 1 in this bit prevents an interrupt when channel 5 has finished a buffe...

Page 188: ... Value 31 0 The GPDMA sets bit 30 in the DMA_Stat Register when this write only register is written This feature is intended to be used by a linked list handling DMA channel to cause an interrupt when it has come to the end of a linked list See the following section for more about this register NA Table 211 DMA Channel 3 External Enable Register DMA3EXTEN 0x8000 5040 Bit Symbol Description Reset V...

Page 189: ...able containing the value read from the Global Enable Register at the time of the previous GPDMA interrupt The ISR should and this variable with the one s complement of the current Global Enable value from step 4 1s in the result identify which channels have been disabled since the last interrupt 6 The ISR can check each channel identified by a 1 in the result of step 5 for having encountered an E...

Page 190: ... can be constructed by having the Next Entry Address of the Nth entry point back to the first entry in the list In such a scheme typically the IRQ Mask bit for buffer completion by the block handling channel would be 0 so that the completion of each block in the list will cause an interrupt Then the ISR or a task activated thereby could fill a completed output buffer with more data or copy the dat...

Page 191: ...ry word transfers the block handling channel s number in the PairedChannel field and 1 in the PairedChannelEnab bit and finally 6 the Enable Register with 1 which starts the list following channel into operation 6 3 Operation of the List Following channel When the list following channel is enabled either by software firmware as described above or when the block handling channel completes a block i...

Page 192: ...bove In the most elegant scheme the ISR and triggered tasks don t move data into or out of the blocks completed by the block transfer channel Instead the buffers are simply added to the end of a list of input buffers to be processed or a list of free output buffers When such a buffer has had its data processed or filled it can be added to the end of the same linked list or a linked list for a diff...

Page 193: ...f data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte contains the slave address and a 1 in the direction bit and is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all rece...

Page 194: ... data is transmitted from the LPC288x I2C interface to a slave device The first byte written to the Tx FIFO is transmitted after a Start condition It contains the slave address of the receiving device 7 bits and 0 in the data direction bit to indicate that data will flow from master to slave After each byte is transmitted the I2C interface samples an acknowledge bit from the slave Start and Stop c...

Page 195: ...e about Master Receive mode see Section 16 8 4 Master Receive mode 5 3 Slave Receive mode In the slave receive mode the I2C interface receives data from an external master transmitter The interface is prepared for slave operation by writing its slave address to the Slave Address Register and enabling the Receive FIFO Not Empty interrupt If the ISR reads an address direction byte with a 1 in the di...

Page 196: ...n master mode R W 0x752E 0x8002 080C I2CLKLO Clock Divisor Low Register The value in this register determines how long the I2C interface waits with the SCL clock low before releasing it to high when it is in master mode R W 0x752E 0x8002 0810 I2ADR Slave Address Register In Slave mode this register contains the address to which the I2C interface responds R W 0x1A 0x8002 0814 I2RFL Receive FIFO Lev...

Page 197: ...is not empty software or a DMA channel can read the oldest byte in the Receive FIFO from this read only register which removes the byte from the FIFO Bit 7 is the first bit received This register should not be read if the Receive FIFO is empty NA Table 217 I2C Transmit Register I2RX 0x8002 0800 Bits Symbol Description Reset value 7 0 The byte to be sent Used only for transmission Bit 7 is sent fir...

Page 198: ... I2TX register 0 4 DRSI Slave Data Request this bit is set when the slave Tx FIFO is empty and the I2C interface is in slave mode and needs data to send It is not set when transmission of a byte is not acknowledged by the master The condition is alleviated and this bit is cleared when software writes data to the I2TXS register 0 5 ACTIVE Active this bit is set by a Start condition and is cleared b...

Page 199: ...TS is 0 0 8 I2RES Software controlling the I2C interface should use a hardware or software timer to detect an erroneous timeout condition on the I2C bus and in such a state write a 1 to this bit to reset the I2C interface This flushes all I2C FIFOs clears the STS register to its reset states and reinitializes internal state machines but does not change the Clock Divisor nor Slave Address registers...

Page 200: ...6 0 This register is only used in slave mode It contains the address which the I2C interface will recognize and respond to 0x1A 31 7 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 223 I2C Rx FIFO Level Register I2RFL 0x8002 0818 Bit Description Reset value 4 0 This read only register contains the number of unread bytes in the R...

Page 201: ...he maximum I2C data rate range of 400 kHz Each register value must be greater than or equal to 4 Table 16 229 gives some examples of I2C bus rates based on PCLK frequency and I2CLKLO and I2CLKHI values Table 226 I2C Tx Byte Count Register I2TXB 0x8002 0824 Bit Description Reset value 6 0 This read only register is cleared whenever the I2C interface becomes active as a transmitter and is incremente...

Page 202: ... both be handled by enabling the Operation Complete and No Acknowledge interrupts plus the Master Data Request interrupt if frames longer than 16 bytes are ever sent or received If there s another master in the application enable the Arbitration Failure interrupt For slave operation the Receive FIFO Not Empty interrupt should be enabled when a master operation loses arbitration and when no master ...

Page 203: ...form the software of the arbitration loss Software should write a 1 to AFI in I2STS to clear the condition set the central state variable to master transmit then add Receive FIFO Not Empty to the interrupts enabled in I2CTL making OCIE NAIE DRMIE ASFIE and RFNE Typically software would then rewrite the frame to I2TX for future retransmission 4 If arbitration is lost in the address direction byte t...

Page 204: ... master transmission and bit 8 1 indicating that a Start condition should be sent before the byte For Master Receive mode this description assumes that the software knows the format of the frame for reading data from the slave Following the address direction byte software or a DMA channel should write I2TX with bytes indicating whether Start conditions should precede or Stop conditions should foll...

Page 205: ...this must be an Operation Complete or Master Data Request interrupt The ISR should read the I2RX register and store the data bytes received from the slave until RFE in I2STS is 1 At this point it should check the OCI bit in I2STS to determine how to proceed If OCI is 0 the current receive frame is not complete and the ISR should write I2TX to control Start and Stop condition generation for future ...

Page 206: ...bled interrupts and write the result back to I2CTL Then it should write as many characters as desired to the Slave Transmit FIFO via the I2TXS register and dismiss the interrupt Any subsequent interrupt with DRSI 1 in I2STS and DRSIE 1 in I2CTL means that the master wants more data than we provided at the last interrupt Once again the ISR should write as many characters as desired to the Slave Tra...

Page 207: ...oller enables 480 or 12 Mbit s data exchange with a USB host controller It includes a USB Controller a DMA Engine and a USB 2 0 ATX PHYsical interface The LPC288x USB controller has eight logical endpoints 0 through 7 Each logical endpoint contains two physical endpoints for IN and OUT packets The USB Controller and DMA Engine each have separate blocks of registers in ARM space The USB Controller ...

Page 208: ...ximum packet size setting by software Supports Soft Connect feature requires an external 1 5k resistor between the CONNECT pin and 3 3V Supports bus powered capability with low suspend current Two DMA channels each assignable to any of 4 physical endpoints Supports Burst data transfers on the AHB Supports Retry and Split transactions on the AHB DDP DD pointer DMA Direct Memory Access EoP End of pa...

Page 209: ...ce pad description Pin name Type Description DP I O USB D pin DM I O USB D pin VBUS Input USB VB sense This pad acts as a voltage sensor rather than a power pad CONNECT Analog I O Used for signalling speed capability indication For high speed USB connect a 1 5K resistor between this pad and 3 3V RREF Reference Transceiver reference Connect a 12K 1 resistor between this pad and ground DCDC_VUSB Pow...

Page 210: ...er the buffer allows for it When the host sends an IN token for an endpoint if the FIFO corresponding to the endpoint is empty the USB Controller returns a NAK otherwise it sends data from the local buffer FIFO For a Slave mode transfer endpoint this also triggers a processor interrupt 6 3 Slave mode transfer Slave data transfer is done via interrupts requested by the USB Controller to the CPU Upo...

Page 211: ...s finished the USB core will assert an end_of_packet signal to the DMA engine through the flow control ports In case of an end_of_transfer the DMA engine stops the data transfer permanently It has to be re programmed for receiving the next packet The DMA engine will raise an interrupt when the transfer is finished successfully it can also raise an interrupt when the transfer encounters an error Th...

Page 212: ... bus reset Master reset includes power on reset and Watchdog reset A bus reset is a unique state of the USB D and D lines both low for 3 ms which a host will assert at the start of connecting a device to the USB Since some register bits are affected differently by the two kinds of reset the following tables that describe particular registers contain Master Reset State and Bus Reset State columns A...

Page 213: ...ation Register 0x8004 1010 USBDCnt USB Data Count Register 0x8004 101C USBData USB Data Port Register 0x8004 1020 USBShort USB Short Packet Register 0x8004 1024 USBECtrl USB Endpoint Control Register 0x8004 1028 USBEIX USB Endpoint Index Register 0x8004 102C USBFN USB Frame Number Register 0x8004 1074 USBScratch USB Scratch Information Register 0x8004 1078 USBUnlock USB Unlock Register 0x8004 107C...

Page 214: ...t value Bus Reset value 0 SOFTCT A 1 in this bit electrically connects the CONNECT pad to the USB_DP pad To use the Soft Connect feature connect a 1 5Kohm resistor between 3 3V and the CONNECT pad 0 NC 1 PWROFF Write a 1 to this bit before placing the LPC288x in low power mode due to USB Suspend state 0 NC 2 WKUP A 1 in this bit enables remote wakeup based on the Remote Wakeup signal 0 0 3 GIE Glo...

Page 215: ...s Reset value 0 BRESET A 1 in this enables interrupt on a Bus Reset from the host 0 NC 1 SOF A 1 in this bit enables interrupt on a Start of Frame SOF or μSOF from the host 0 0 2 PSOF A 1 in this bit enables interrupt on a Pseudo Start of Frame PSOF or μPSOF from the host 0 0 3 SUSP A 1 in this bit enables interrupt when the host changes the state of the bus from active to suspend 0 0 4 RESUME A 1...

Page 216: ...cted a Bus Reset from the host 0 1 1 SOF A 1 in this bit indicates that the USB controller has received a Start of Frame SOF or μSOF from the host 0 0 2 PSOF A 1 in this bit indicates that the USB controller has received a Pseudo Start of Frame PSOF or μΠSOF from the host 0 0 3 SUSP A 1 in this bit indicates that the host has changed the state of the bus from active to suspend 0 0 4 RESUME A 1 in ...

Page 217: ...1 to this bit to clear the Start of Frame interrupt 2 CLRPSOF Write a 1 to this bit to clear the Pseudo Start of Frame interrupt 3 CLRSUSP Write a 1 to this bit to clear the Suspend interrupt 4 CLRRESUME Write a 1 to this bit to clear the Resume interrupt 5 CLRHS_STAT Write a 1 to this bit to clear the HS interrupt 6 CLRDMA Write a 1 to this bit to clear the interrupt for a change in any of the US...

Page 218: ... 0 as it is after either Reset an enabled Suspend interrupt sets request 0 to the interrupt controller If this bit is 1 it sets request 1 0 0 4 RESUME1 When this bit is 0 as it is after either Reset an enabled Resume interrupt sets request 0 to the interrupt controller If this bit is 1 it sets request 1 0 0 5 HS_STAT1 When this bit is 0 as it is after either Reset an enabled HS Status interrupt se...

Page 219: ...how ACK STALL NYET and NAK events request interrupt on OUT endpoints other than Endpoint 0 00 Interrupt on all ACK STALL NYET and NAK events 01 Interrupt on ACK STALL and NYET events 1x Interrupt on ACK STALL and NYET events and on the first NAK event in response to an IN or OUT token after a previous ACK response 11 11 5 4 DDBG_M_IN Data Debug Mode In these bits control how ACK and NAK events req...

Page 220: ...d They remain write protected after operation is Resumed Write 0xAA37 to this write only register to unlock the USB Controller registers for writing Table 242 USB Frame Number Register USBFN 0x8004 1074 Bit Symbol Description Master Reset value Bus Reset value 10 0 SOF Frame number 0 0 13 11 mSOF mSOF number 0 0 31 14 Reserved The values read from reserved bits is not defined Table 243 USB Scratch...

Page 221: ...xPacketSize register before the endpoint is enabled To access this register the Endpoint Index register must be written first with the target endpoint number Table 245 USB Endpoint Index Register USBEIX 0x8004 102C Bit Symbol Description Master Reset value Bus Reset value 0 DIR If the SEL_EP0SET bit in this register is 0 a 1 in this bit selects IN endpoint identified by the ENDPIDX field of this r...

Page 222: ...trol Endpoint 01 Isochronous Endpoint 10 Bulk Endpoint 11 Interrupt Endpoint 0 0 2 DBLBUF A 1 in this bit enables double buffering for the endpoint selected by the USBEIX register A 0 selects single buffer mode 0 0 3 EP_ENAB A 1 in this bit enables the endpoint selected by the USBEIX register and allocates buffers in the USB RAM in accordance with the MaxPacketSize value 0 disables the endpoint Wr...

Page 223: ...2 TO_DATA This bit only applies to Control Endpoint 0 When a SETUP token is received for this endpoint write a 1 to this bit to move to the data phase of the control transfer 0 0 3 Reserved software should not write ones to reserved bits The values read from reserved bits is not defined 4 CLRBUF Select an OUT endpoint in the USBEIX register then write a 1 to this bit to clear its RX buffer The RX ...

Page 224: ...FIFOSize Writing this field sets the FIFO size in bytes for the endpoint selected by the USBEIX register The value written to this frame should be the same as the value indicated to the host during the enumeration process Because the maximum packet size is a function of the type of endpoint and the mode HS FS this register will typically need to be re programmed when a shift between HS and FS mode...

Page 225: ...ture IN token for the endpoint The value written to this field may not be larger than the Max Packet Size for the endpoint Writing zero to this field results in the transmission of one empty packet This field is automatically loaded with the value in the endpoint s Max Packet Size Register when the host ACKs the IN packet For an OUT RX endpoint the hardware loads this field with the number of rece...

Page 226: ...r are 00 otherwise it is considered to contain the number of bytes in those 2 LSbits in the LSbytes of the value written Software may have to shift the data to accommodate this convention For an OUT RX endpoint that doesn t use a DMA channel write the USBEIX register to select the endpoint then read the Data Count Register to determine the number of bytes in the buffer then read that many bytes fr...

Page 227: ...rupts from OUT Endpoint 2 0 0 5 EP2TXIE A 1 in this bit enables TX interrupts from IN Endpoint 2 0 0 6 EP3RXIE A 1 in this bit enables RX interrupts from OUT Endpoint 3 0 0 7 EP3TXIE A 1 in this bit enables TX interrupts from IN Endpoint 3 0 0 8 EP4RXIE A 1 in this bit enables RX interrupts from OUT Endpoint 4 0 0 9 EP4TXIE A 1 in this bit enables TX interrupts from IN Endpoint 4 0 0 10 EP5RXIE A ...

Page 228: ...ffer is emptied This bit is enabled set and cleared as described for bit 0 0 0 6 EP3RX This bit is set when the Endpoint 3 OUT RX buffer is filled This bit is enabled set and cleared as described for bit 0 0 0 7 EP3TX This bit is set when the Endpoint 3 IN TX buffer is emptied This bit is enabled set and cleared as described for bit 0 0 0 8 EP4RX This bit is set when the Endpoint 4 OUT RX buffer i...

Page 229: ...he endpoint 1 Transmit interrupt 0 0 4 CLR2RX Write a 1 to this bit to clear the endpoint 2 Receive interrupt 0 0 5 CLR2TX Write a 1 to this bit to clear the endpoint 2 Transmit interrupt 0 0 6 CLR3RX Write a 1 to this bit to clear the endpoint 3 Receive interrupt 0 0 7 CLR3TX Write a 1 to this bit to clear the endpoint 3 Transmit interrupt 0 0 8 CLR4RX Write a 1 to this bit to clear the endpoint ...

Page 230: ...t to set the endpoint 1 Receive interrupt 0 0 3 SET1TX Write a 1 to this bit to set the endpoint 1 Transmit interrupt 0 0 4 SET2RX Write a 1 to this bit to set the endpoint 2 Receive interrupt 0 0 5 SET2TX Write a 1 to this bit to set the endpoint 2 Transmit interrupt 0 0 6 SET3RX Write a 1 to this bit to set the endpoint 3 Receive interrupt 0 0 7 SET3TX Write a 1 to this bit to set the endpoint 3...

Page 231: ...t 0 to the interrupt controller If this bit is 1 it sets request 1 0 0 5 P2TX When this bit is 0 as it is after either Reset an enabled TX interrupt from IN endpoint 2 sets request 0 to the interrupt controller If this bit is 1 it sets request 1 0 0 6 P3RX When this bit is 0 as it is after either Reset an enabled RX interrupt from OUT endpoint 3 sets request 0 to the interrupt controller If this b...

Page 232: ...rity Register USBEIntP 0x8004 10A8 Bit Symbol Description Master Reset value Bus Reset value Table 257 USB Test Mode Register USBTMode 0x8004 1084 Bit Symbol Description Master Reset value Bus Reset value 0 SE0NAK A 1 in this bit sets the D and D lines to a HS Quiescent state In this mode the USB controller only responds to a valid IN token and always responds with a NAK 0 0 1 JSTATE A 1 in this b...

Page 233: ...ress Register 0x8004 000C UDMA0Throtl USB DMA Channel 0 Throttle Register 0x8004 0010 UDMA0Cnt USB DMA Channel 0 Count Register 0x8004 0014 UDMA1Stat USB DMA Channel 1 Status Register 0x8004 0040 UDMA1Ctrl USB DMA Channel 1 Control Register 0x8004 0044 UDMA1Src USB DMA Channel 1 Source Address Register 0x8004 0048 UDMA1Dest USB DMA Channel 1 Destination Address Register 0x8004 004C UDMA1Throtl USB...

Page 234: ... When a channel is software reset all of the registers for the channel are cleared to their Reset values DMA activity stops except that if a transfer is in progress at the time of the reset it is completed and the DMA channel s FIFO is cleared Table 260 USB DMA Control Register UDMACtrl 0x8004 0400 Bit Symbol Description Reset value 0 UDMA_EN A 1 in this bit enables USB DMA operation Changing this...

Page 235: ...nnel Or this problem can be avoided by disabling interrupts before reading this register and re enabling them after the DMA channel is programmed and made Busy Table 262 USB DMA Status Register UDMAStat 0x8004 0408 Bit Symbol Description Reset value 2 0 CH0Stat 000 Idle channel 0 is not involved in the execution of a DMA transfer 001 Busy channel 0 is involved in the execution of a DMA transfer 01...

Page 236: ... a DMA transfer 01 Busy this channel is involved in execution of a DMA transfer 10 Suspend this channel was suspended during its DMA transfer 11 Error an error occurred during this channel s DMA transfer 0 15 2 Reserved The values read from reserved bits is not defined 16 Write Error This bit is 1 if an error e g bus error occurred while writing data to the destination 0 17 Dest FC Error This bit ...

Page 237: ...t when DMA channel 0 aborts a DMA transfer because of an error and the IError_En bit in its Control Register is 1 Software can clear this bit by writing a 1 to bit 2 of the UDMAIntClr Register and can set this bit by writing a 1 to bit 2 of the UDMAIntSet Register 0 4 3 Reserved The values read from reserved bits is not defined 5 CH1IEOT This bit is set when DMA channel 1 successful completes a DM...

Page 238: ... to this bit to enable Error interrupts for DMA channel 1 When this register is read a 1 in this bit indicates that Error interrupts are enabled for DMA channel 1 0 31 7 Reserved software should not write ones to reserved bits The values read from reserved bits is not defined Table 266 USB DMA Interrupt Disable Register UDMAIntDis 0x8004 0420 Bit Symbol Description Reset value 0 Reserved software ...

Page 239: ...terrupt service routine should write a 1 to this bit to clear the EOT interrupt for DMA channel 0 0 2 CH0IErrorClr A USB DMA interrupt service routine should write a 1 to this bit to clear the Error interrupt for DMA channel 0 0 4 3 Reserved software should not write ones to reserved bits 5 CH1IEOTClr A USB DMA interrupt service routine should write a 1 to this bit to clear the EOT interrupt for D...

Page 240: ...RX transfers 1x reserved do not write 00 14 11 SFC_PORT 0000 OUT endpoint 1 0001 IN endpoint 1 0010 OUT endpoint 2 0011 IN endpoint 2 0100 1111 reserved do not write 0 16 15 DEST 00 use for OUT RX transfers 01 use for IN TX transfers 1x reserved do not write 0 18 17 DTYPE must be 10 to select 32 bit transfers 10 20 19 DA_ADJ 00 fixed destination address use for IN TX transfers 01 destination addre...

Page 241: ...nsfer Memory address for an IN TX transfer bits 1 0 must be 00 or a Configuration Error results For an IN TX transfer reading this register returns the word address just above the last data that was successfully read This is true both during the transfer and after it completes 0 Table 271 USB DMA Channel Destination Address Registers UDMA0Dest 0x8004 000C and UDMA1Dest 0x8004 004C Bit Symbol Descr...

Page 242: ...OUT RX transfer source flow control is used Programming an SThrottle value of 1 is recommended as that will allow the other USB DMA channel to access memory between each word that this channel transfers Writing this register while the USB DMA channel is enabled will stop the channel and set its status error field to Update Error 8 45 USB DMA Flow Control Port Registers UDMAFCP0 0x8004 0500 UDMAFCP...

Page 243: ...us Reset software firmware should do the following 1 Write the Device Address Register Section 17 8 4 to enable the USB Controller at address 0 2 Write the Endpoint Index Register Section 17 8 15 to select Endpoint 0 Setup 3 Write the Endpoint Control Register Section 17 8 17 and or Endpoint Type Register Section 17 8 16 to enable the host to send the address packet 4 Write the Interrupt Enable Re...

Page 244: ...X endpoint in Interrupt slave mode Suppose that an endpoint interrupt occurs when an IN token is NAKed Software firmware should do the following 1 Write the Endpoint Index Register to select the IN Endpoint 2 Write the Data Count Register Section 17 8 19 with the number of bytes in the packet 3 Write the Data Port Registers Section 17 8 20 the appropriate number of times to send the packet data An...

Page 245: ...ction 17 8 44 for an IN TX transfer 4 Write the channel s Count Register Section 17 8 43 with the number of bytes to send 5 If desired write the DMA Interrupt Enable Register Section 17 8 36 to enable interrupt from the channel 6 Write the channel s Control Register Section 17 8 40 appropriately for an IN TX transfer from the selected endpoint number with a non zero CHEN field and optionally to re...

Page 246: ...on requires 11 of these clocks 3 Pin description Table 18 275 gives a brief summary of the pads related to the ADC UM10208 Chapter 18 Analog to Digital Converter ADC Rev 02 1 June 2007 User manual Table 275 A D pin description Pin Type Description AIN4 0 Input Analog Inputs These are dedicated pads with no digital I O capability Unused pins can be left unconnected DCDC_Vbat Input This pad is inter...

Page 247: ...bits representing the fraction of the voltage on ADC_VDD that was sampled on DCDC_Vbat RO 0 0x8000 2414 ADCCON Control Register This register contains four control bits and one status bit R W 0 0x8000 2420 ADCSEL Select Register This register selects which of the 6 inputs are scanned and converted and also selects the resolution accuracy of the conversion for each R W 0 0x8000 2424 ADCINTE Interru...

Page 248: ...onversion then immediately write a 0 to this bit with the same values of ENABLE and CSCAN 4 ADCBUSY This read only bit is 1 when an ADC conversion is in progress It is cleared when the CSCAN bit is 0 and the ADC completes conversion of the input s selected by ADCSEL To terminate continuous conversion first write 0 to CSCAN then wait for this bit to be 0 Power down mode is not entered until this bi...

Page 249: ... Reserved The value read from a reserved bit is not defined Table 280 A D Interrupt Enable Register ADCINTE 0x8000 2428 Bit Symbol Description Reset value 0 INTENAB If this bit is 0 as it is after reset the ADC does not request an interrupt at the completion of conversion of the analog input s selected by the ADCSEL register Write a 1 to this bit to enable an interrupt at that time 0 31 1 Reserved...

Page 250: ...e ADCINTC register 6 Read the Result register s for the analog input s that were converted 5 3 Continuous mode conversion 1 Write the ADCSEL register to select which analog input s is are to be converted and the number of result bits desired for each 2 Write the ADCCON register with 1s in the ENABLE CSCAN and START bits 3 Write the ADCCON register with 1s in the ENABLE and CSCAN bits but 0 in the ...

Page 251: ...ous mode conversion 1 Write the ADCCON register with a 1 in the ENABLE bit but 0s in the CSCAN and START bits 2 Either poll the STATUS bit in the ASCCON register until it is 1 or wait for an interrupt 3 If interrupt driven write 1 to the ADCINTC register 4 If necessary read the Result register s for the analog input s that were converted in this last scan ...

Page 252: ...er can be performed by the processor or by GPDMA channel s 3 DAI pins The DAI has three dedicated pins as shown in Table 19 284 4 DAI registers Table 19 285 lists the LPC288x registers associated with I2S input Subsequent sections describe the registers in greater detail UM10208 Chapter 19 I2S input module DAI Rev 02 1 June 2007 User manual Table 284 DAI pins Name Type Description BCKI P3 1 I O Bi...

Page 253: ... 1 or 2 DMA channels Table 286 Stream I O Configuration Register SIOCR 0x8020 0384 Bit s Name Description Reset value 6 0 Reserved Always write 1s to these bits 0 7 DAI_OE Write 0 to this bit if the DAI should operate in Slave mode with the BCKI and WSI pins as inputs Write 1 to this bit if the DAI should operate in Master mode with the BCKI and WSI pins as outputs 1 31 8 Reserved Always write 0s ...

Page 254: ... 31 24 read as zero RO 0 R24IN1 0x8020 000C The oldest R channel value in the SAI can be read from this register The value is removed from the R FIFO by reading this register Bits 31 24 read as zero RO 0 SAISTAT1 0x8020 0010 The current status of the SAI can be read from this register Writing any value to this address clears the underrun and overrun bits in this register R W 0 SAIMASK1 0c8020 0014...

Page 255: ...ty 0 31 10 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 290 SAI1 Mask Register SAIMASK1 0x8020 0014 Bit Name Description Reset Value 0 RUNMK If this bit is 0 the R channel underrun condition is enabled to cause an SAI interrupt request 1 1 LUNMK If this bit is 0 the L channel underrun condition is enabled to cause an SAI inte...

Page 256: ...rovide the proper DAI clocking In Slave mode the external I2S bit clock arrives on the BCKI pin program the CGU to route this clock to its DAI_XBCK output In Master mode program the CGU to generate the bit clock and route it to its DAI_BCKI output and program a fractional divider to divide that bit clock by twice the number of bits per word in stretched mode and route the fractional divider output...

Page 257: ...uld be stored and store the word in the R buffer which may be the same as the L buffer If LFULMK is 0 do this 4 times then read SAISTAT1 check LOVER and ROVER then dismiss the interrupt If LHALFMK is 0 do this twice then read SAISTAT1 check LOVER and ROVER and loop back to read and store more words as long as LNOTMT is 1 If LNMTMK is 0 do this once then read SAISTAT1 check LOVER and ROVER and loop...

Page 258: ... buffers for the L and R channels Write the address of the L24IN1 register to the Source Address register of one DMA channel and the address of the R24IN1 register to the other channel s Source Address register and program both channels to transfer words 16 bit values must be stored in separate buffers If the SAI s DMA request is based on the FIFO being half full write the address of the L32IN1 re...

Page 259: ...AO This transfer can be performed by the processor or by GPDMA channel s 3 DAO pins The DAO has three dedicated pins as shown in Table 20 292 4 DAO registers Table 20 293 lists the LPC288x registers associated with I2S output Subsequent sections describe the registers in greater detail UM10208 Chapter 20 I2S output module DAO Rev 02 1 June 2007 User manual Table 292 DAO pins Name Type Description ...

Page 260: ...with each entry containing two 24 bit values Table 294 Stream I O Configuration Register SIOCR 0x8020 0384 Bit s Name Description Reset value 6 0 Reserved Always write 1s to these bits 0 7 DAI_OE This bit affects the I2S Input module DAI See Section 19 4 1 on page 253 1 31 8 Reserved Always write 0s to these bits The value read from reserved bits is not defined Table 295 Stream I O Configuration R...

Page 261: ... register Bits 31 24 are ignored when this register is written WO 0 R24OUT1 0x8020 020C One 24 bit value can be written to the R channel FIFO via this register Bits 31 24 are ignored when this register is written RO 0 SAOSTAT1 0x8020 0210 The current status of the SAO can be read from this register Writing any value to this address clears the underrun and overrun bits in this register R W 0 SAOMAS...

Page 262: ...its The value read from a reserved bit is not defined Table 298 SAO1 Mask Register SAOMASK1 0x8020 0214 Bit Name Description Reset Value 0 RUNMK If this bit is 0 the R channel underrun condition is enabled to cause an SAI interrupt request 1 1 LUNMK If this bit is 0 the L channel underrun condition is enabled to cause an SAI interrupt request 1 2 ROVMK If this bit is 0 the R channel overrun condit...

Page 263: ...per word in stretched mode and route the fractional divider output to its DAO_WS output 4 Write the SAO1 Interrupt Request register in the interrupt controller INT_REQ20 0x8030 0460 to enable SAO1 interrupts at the desired priority level see Section 9 5 1 on page 121 5 Write the SAO1 Mask register with zero es in the desired interrupt condition s For fully interrupt driven applications write a 0 t...

Page 264: ...4OUT1 Whenever values wider than 16 bits are available in the buffer s these are the register s to write If L data wider than 16 bits is available read a word from the L buffer and write it to L24OUT1 If R data wider than 16 bits is available read a word from the R buffer which may be the same as the L buffer and write it to R24OUT1 If LMTMK is 0 do this 4 times then read SAOSTAT1 check LUNDER and...

Page 265: ... Destination Address register and program both channels to transfer words 16 bit values are available for both channels in separate buffers If the SAO s DMA request is based on the FIFO being half empty write the address of the L32OUT1 register to the Destination Address register of one DMA channel and the address of the R32OUT1 register to the other channel s Destination Address register and prog...

Page 266: ...differential converter SD the output of which goes to an ADC The output of each ADC is a bitstream at 128 fs where fs is the Nyquist sample frequency Decimators then converts these bitstreams to 24 bit parallel format clocked at the sample rate Each decimator block also includes DC blocking digital filters in its input and output stages as well as a digital gain control that can be used as a volum...

Page 267: ...e The last two rows can be extrapolated to smaller voltage ranges and higher gain settings although signal to noise ratios will degrade 4 Dual ADC Block Diagrams Figure 21 28 shows how the Dual ADC and its supporting modules are connected Figure 21 29 shows further detail of the Decimator block 5 Dual ADC registers Table 21 302 lists the LPC288x registers that are associated with the Dual ADC and ...

Page 268: ...trol bits for the decimator block R W 0 DECSTAT 0x8020 03B0 Decimator Status Register This read only register contains the status of the decimator RO 0 Table 303 Stream I O Configuration Register SIOCR 0x8020 0384 Bit s Name Description Reset value 6 0 Reserved Always write 1s to these bits 0 7 DAI_OE This bit affects the I2S Input module DAI See Section 19 4 1 on page 253 1 31 8 Reserved Always w...

Page 269: ...20 03A4 Bit s Name Description Reset value Table 305 Dual ADC Control Register DADCCTRL 0x8020 03A8 Bit s Name Description Reset Value 0 Reserved Always write a 1 to this bit 0 1 RDITHER If this bit is 1 dither is applied to the RADC 0 2 Reserved Always write a 0 to this bit 0 3 RPD A 1 in this bit powers down the RADC 0 4 Reserved Always write a 1 to this bit 0 5 LDITHER If this bit is 1 dither i...

Page 270: ...ENIDCBF A 1 in this bit enables the input blocking DC filter 0 21 Reserved Always write 0 to this bit 0 22 ENTIMER A 1 in this bit enables the timer after reset See step 5 in Section 21 7 1 Setting up the dual ADC and SAI4 on page 273 0 31 23 Reserved always write 0s to these bits The values read from reserved bits are not defined Table 307 Decimator status register DECSTAT 0x8020 03B0 Read Only B...

Page 271: ...he oldest L channel value in the SAI can be read from this register The value is removed from the L FIFO by reading this register Bits 31 24 read as zero RO 0 R24IN4 0x8020 018C The oldest R channel value in the SAI can be read from this register The value is removed from the R FIFO by reading this register Bits 31 24 read as zero RO 0 SAISTAT4 0x8020 0190 The current status of the SAI can be read...

Page 272: ...not empty 0 31 10 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 310 SAI4 Mask Register SAIMASK4 0x8020 0194 Bit Name Description Reset Value 0 RUNMK If this bit is 0 the R channel underrun condition is enabled to cause an SAI interrupt request 1 1 LUNMK If this bit is 0 the L channel underrun condition is enabled to cause an S...

Page 273: ...disables the Decimator from sending values to SAI4 until its outputs are valid Table 21 311 below shows the delay as a function of whether the two DC blocking filters are enabled 6 Write the SAI4 Interrupt Request register in the interrupt controller INT_REQ19 0x8030 044C to enable SAI4 interrupts at the desired priority level see Section 9 5 1 on page 121 7 Write the SAI4 Mask register with zero ...

Page 274: ...mic DMA assignment One or two GPDMA channel s is are selected and configured when the application determines that dual ADC conversion should be done These modes are identical to those described earlier in this manual for the I2S input SAI See Section 19 6 Programming the DAI and SAI1 on page 256 for descriptions of how to program these modes ...

Page 275: ...r which the digital results are converted to analog voltages It includes several advanced features such as digital de emphasis digital gain control muting and polarity control that are described in the following sections Figure 22 30 shows the block diagram of the Dual DAC module The interpolation from 1 fs to 128 fs is realized in four steps 1 The first stage is a 99 tap halfband filter HB which ...

Page 276: ...l always lie between those on VREFN and VREFP The recommended interface to the output pins for output frequencies in the audio range includes a series capacitor of about 22 uF a 3 3 nF post filter capacitor to ground on the pin side of the series cap and a 10K pulldown resistor to ground on the destination side of the series cap 4 Registers Table 22 313 shows the registers that relate to the Dual ...

Page 277: ... Description Reset Value 7 0 RGAIN This field controls the negative gain volume level of the right channel Values 0 200 select 0 thru 50 dB in steps of 0 25 dB Values above 200 select negative gain as follows 1100 1000 50 0 dB 1100 1100 53 0 dB 1101 0000 56 0 dB 1101 0100 58 9 dB 1101 1000 62 0 dB 1101 1100 65 2 dB 1110 0000 68 0 dB 1110 0100 71 2 dB 1110 1000 73 4 dB 1100 1100 76 3 dB 1111 0000 8...

Page 278: ...s in this field and the MODE field Do not program combinations other than those shown 0 24 PSLOW This field controls how long the Dual DAC takes to power up and down 0 selects 512 fs periods 1 selects 1024 fs periods 0 25 DDAC_PD A 1 in this bit powers down the interpolator Setting this bit as described in Section 22 6 3 Power down procedure on page 282 automatically invokes the same soft muting o...

Page 279: ...TRL This bit is cleared by a non zero input value 0 3 LSILENT When the ENSILDET bit in DDACCTRL is 1 this bit will be set when the left channel detects the number of consecutive all zero input values indicated by the SILDET_T field in DDACCTRL This bit is cleared by a non zero input value 31 4 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not d...

Page 280: ...this register is written WO 0 L24OUT2 0x8020 0288 One 24 bit value can be written to the L channel FIFO via this register Bits 31 24 are ignored when this register is written WO 0 R24OUT2 0x8020 028C One 24 bit value can be written to the R channel FIFO via this register Bits 31 24 are ignored when this register is written WO 0 SAOSTAT2 0x8020 0290 The current status of the SAO can be read from th...

Page 281: ...e value read from a reserved bit is not defined Table 321 SAO2 Mask Register SAOMASK2 0x8020 0294 Bit Name Description Reset Value 0 RUNMK If this bit is 0 the R channel underrun condition is enabled to cause an SAI interrupt request 1 1 LUNMK If this bit is 0 the L channel underrun condition is enabled to cause an SAI interrupt request 1 2 ROVMK If this bit is 0 the R channel overrun condition is...

Page 282: ...e interrupt controller INT_REQ21 0x8030 0464 to enable SAO2 interrupts at the desired priority level see Section 9 5 1 on page 121 6 Write the SAO2 Mask register with zero es in the desired interrupt condition s For fully interrupt driven applications write a 0 to the LMTMK or LHALFMK bit or RMTMK or RHALFMK if only the R channel is used For DMA operation write a 0 to LUNDER and or RUNDER to allow...

Page 283: ... interrupt driven All dual DAC data is handled via interrupts 2 Dedicated DMA All dual DAC input data is fetched from memory by one or two dedicated GPDMA channel s 3 Dynamic DMA assignment One or two GPDMA channel s is are selected and configured when the application determines that dual DAC output should be done These modes are identical to those described earlier in this manual for the I2S outp...

Page 284: ...ecure digital memory card bus host It can be connected to several multimedia cards or a single secure digital memory card DMA transfers are supported through the GP DMA facility 3 SD MMC card interface pin description An additional signal is needed for the interface in some cases a power control line called MCIPWR This function can be generated from any available pin such as a GPIO whose level can...

Page 285: ...for a secure digital memory card MCMD A bidirectional command channel that initializes a card and transfers commands CMD has two operational modes Open drain for initialization Push pull for command transfer MD0 A bidirectional data channel operating in push pull mode 4 2 Secure Digital memory card Figure 23 32 shows the Secure Digital memory card connection 4 2 1 Secure Digital memory card bus si...

Page 286: ...ol unit Command path Data path Data FIFO 4 3 1 Adapter register block The adapter register block contains all MCI SD registers This block also generates the signals that clear the static flags in the multimedia card The clear signals are generated when a 1 is written into the corresponding bit location of the MCIClear register 4 3 2 Control unit The control unit contains the power management funct...

Page 287: ...r the IDLE phase 4 3 3 Command path The command path subunit sends commands to and receives responses from the cards 4 3 4 Command path state machine When the command register is written to and the enable bit is set command transfer starts When the command has been sent the Command Path State Machine CPSM sets the status flags and enters the IDLE state if a response is not required If a response i...

Page 288: ...nd path operates in a half duplex mode so that commands and responses can either be sent or received If the CPSM is not in the SEND state the MCICMD output is in hi Z Z state as shown in Figure 23 35 Data on MCICMD is synchronous to the rising MCICLK edge All commands have a fixed length of 48 bits Table 23 323 shows the command format The MCI adapter supports two response types Both use CRC error...

Page 289: ...rst 120 bits of CID or CSD for the long response format Note that the start bit transmitter bit and the six reserved bits are not used in the CRC calculation The CRC checksum is a 7 bit value CRC 6 0 Remainder M x x7 G x G x x7 x3 1 M x start bit x39 last bit before CRC x0 or M x start bit x119 last bit before CRC x0 Table 324 Simple response format Bit Position Width Value Description 0 1 1 End b...

Page 290: ...te and the data path subunit starts receiving data from a card 4 3 7 Data path state machine The DPSM operates at MCICLK frequency Data on the card bus signals is synchronous to the rising edge of MCICLK The DPSM has six states as shown in Figure 23 36 IDLE The data path is inactive and the MD3 0 outputs are in hi Z When the data control register is written and the enable bit is set the DPSM loads...

Page 291: ...e asserted and moves to the SEND state Note The DPSM remains in the WAIT_S state for at least two clock periods to meet Nwr timing constraints SEND The DPSM starts sending data to a card Depending on the transfer mode bit in the data control register the data transfer mode can be either block or stream In block mode when the data block counter reaches zero the DPSM sends an internally generated CR...

Page 292: ...n all data signals on the same clock edge while receiving data the DPSM sets the start bit error flag and moves to the IDLE state The data path also operates in half duplex mode where data is either sent to a card or received from a card While not being transferred MD3 0 are in the hi Z state Data on these signals is synchronous to the rising edge of the clock period If wide mode is not selected t...

Page 293: ... the FIFO can be disabled transmit enabled or receive enabled TxActive and RxActive are mutually exclusive The transmit FIFO refers to the transmit logic and data buffer when TxActive is asserted see Transmit FIFO The receive FIFO refers to the receive logic and data buffer when RxActive is asserted see Receive FIFO Table 328 Data path status flags Flag Description TxFifoFull Transmit FIFO is full...

Page 294: ...o by the current value of the read pointer is driven to the APB The read pointer is incremented when the APB interface asserts an acknowledge signal If the receive FIFO is disabled all status flags are de asserted and the read and write pointers are reset The data path subunit asserts RxActive when it receives data Table 23 330 lists the receive FIFO status flags Table 329 Transmit FIFO status fla...

Page 295: ...own in Table 23 331 1 Reset Value reflects the data stored in used bits only It does not include reserved bits content Table 331 SD MCI register map Name Description Access Width Reset Value 1 Address MCIPower Power control register R W 8 0x00 0x8010 0000 MCIClock Clock control register R W 12 0x000 0x8010 0004 MCIArgument Argument register R W 32 0x00000000 0x8010 0008 MCICommand Command register...

Page 296: ...es are assigned to all cards Table 332 Power Control register MCIPower 0x8010 0000 Bit Symbol Description Reset Value 1 0 Ctrl 00 Power off 01 Reserved 10 Power up 11 Power on 00 5 2 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 6 OpenDrain MCICMD output control 0 31 7 Reserved user software should not write ones to reserved bits Th...

Page 297: ...he CPSM Table 23 335 shows the MCICommand register Note After a data write data cannot be written to this register for three MCLK clock periods plus two PCLK clock periods Table 23 336 shows the response types Table 334 Argument register MCIArgument 0x8010 0008 Bit Symbol Description Reset Value 31 0 CmdArg Command argument 0x0000 0000 Table 335 Command register MCICommand 0x8010 000C Bit Symbol D...

Page 298: ... register contains the data timeout period in card bus clock periods Table 23 340 shows the MCIDataTimer register A counter loads the value from the data timer register and starts decrementing when the Data Path State Machine DPSM enters the WAIT_R or BUSY state If the timer reaches 0 while the DPSM is in either of these states the timeout status flag is set A data transfer must be written to the ...

Page 299: ...ot necessary to clear the enable bit after the data transfer BlockSize controls the data block length if Mode is 0 as shown in Table 23 343 Table 341 Data Length register MCIDataLength 0x8010 0028 Bit Symbol Description Reset Value 15 0 DataLength Data length value 0x0000 31 16 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 342...

Page 300: ...state of the underlying logic for example FIFO full and empty flags are asserted and de asserted as data while written to the FIFO Table 23 345 shows the MCIStatus register n 2 10 2n bytes 11 211 2048 bytes 12 15 Reserved Table 343 Data Block Length Block size Block length Table 344 Data Counter register MCIDataCnt 0x8010 0030 Bit Symbol Description Reset Value 15 0 Remaining data 0x0000 31 16 Res...

Page 301: ...ress 0 14 TxFifoHalfEmpty Transmit FIFO half empty 0 15 RxFifoHalfFull Receive FIFO half full 0 16 TxFifoFull Transmit FIFO full 0 17 RxDataAvlbl Data available in receive FIFO 0 18 TxFifoEmpty Transmit FIFO empty 0 19 RxFifoFull Receive FIFO full 0 20 TxDataAvlbl Data available in transmit FIFO 0 21 RxFifoEmpty Receive FIFO empty 0 31 22 Reserved user software should not write ones to reserved bi...

Page 302: ... CmdTimeOut flag 0 3 Mask3 Mask DataTimeOut flag 0 4 Mask4 Mask TxUnderrun flag 0 5 Mask5 Mask RxOverrun flag 0 6 Mask6 Mask CmdRespEnd flag 0 7 Mask7 Mask CmdSent flag 0 8 Mask8 Mask DataEnd flag 0 9 Mask9 Mask StartBitErr flag 0 10 Mask10 Mask DataBlockEnd flag 0 11 Mask11 Mask CmdActive flag 0 12 Mask12 Mask TxActive flag 0 13 Mask13 Mask RxActive flag 0 14 Mask14 Mask TxFifoHalfEmpty flag 0 15...

Page 303: ...0BC The receive and transmit FIFOs can be read or written as 32 bit wide registers The FIFOs contain 16 entries on 16 sequential addresses This allows the microprocessor to use its load and store multiple operands to read write to the FIFO Table 23 349 shows the MCIFIFO register Table 349 Data FIFO register MCIFIFO 0x8010 0080 00BC Bit Symbol Description Reset Value 31 0 FIFO data 0x0000 0000 ...

Page 304: ...for communication with serial interface devices 3 LCD interface pins Table 24 350 describes the pins associated with the LCD interface If the LCD interface is not used the pins can be programmed to be general purpose I O UM10208 Chapter 24 LCD controller Rev 02 1 June 2007 User manual Table 350 LCD Interface Pins Name Type Description LD7 0 I O Bidirectional data bus or serial clock and data Since...

Page 305: ...and Register Writing to this register switches the data bus from write output to read input mode The units bit of the data written controls the instruction data signal WO 0x8010 3014 LCDIBYTE Instruction Byte Register Writing to this register places one byte in the output FIFO tagged as an instruction byte When the bus is in read input mode and the BUSY status bit is 0 software can read the byte r...

Page 306: ...makes the hardware read a status register between data transfers and delay data transfer until a status bit allows it 0 9 CBSENSE If CBUSY is 1 this bit determines which state of the bit selected by the BUSYN field the hardware will wait for before transferring data If this bit is 0 the hardware polls until the selected bit is 1 high while if this bit is 1 the hardware polls until the selected bit...

Page 307: ... not been completed 0 9 5 FIFOLEV This field contains the number of bytes currently in the output FIFO Zero means the FIFO is empty 0 31 10 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 354 Raw Interrupt Status Register LCDISTAT 0x8010 0008 Read Only Bit Symbol Description Reset value 0 LCDFIFOMT This bit is 1 if the output FI...

Page 308: ...aining less than 8 bytes n a 2 LCDOVER Writing a 1 to this bit clears bit 2 in LCDSTAT thus clearing an interrupt request caused by software writing more data to the output FIFO than it can hold n a 3 LCDREAD Writing a 1 to this bit clears bit 3 in LCDSTAT thus clearing an interrupt request caused by the completion of a read operation n a 31 4 Reserved user software should not write ones to reserv...

Page 309: ...ints Table 359 Data Byte Register LCDDBYTE 0x8010 3030 Bit Symbol Description Reset value 7 0 Writing to this register places this byte in the output FIFO tagged as a data byte After reading has been initiated and bit 4 of the LCDSTAT register has gone from 1 to 0 the byte from the remote device can be read from this register or equivalently LCDIBYTE 0 31 8 Reserved user software should not write ...

Page 310: ... is desired when the read operation is complete clear bit 3 in the LCDIMASK register if it s not already 0 to enable such an interrupt 2 Write to the LCDREAD register Write 0 to read the instruction register with LRS low write 1 to read the data register with LRS high 3 Wait for an interrupt with bit 3 of LCDSTAT set or poll the LCDISTAT register until bit 3 is 1 4 Read LCDIBYTE or LCDDBYTE to get...

Page 311: ...busy bit and reading or writing to a data register Unless the remote device has its instruction register at the output side of the same address from which its status register is read LRS can t be used in both ways If the remote device has more than one address pin used to select registers for input and output GP output pins must be used to drive some or all of the address pins Wait at least 7 LCD ...

Page 312: ...e listed alphabetically except that digital supply pins are last Within each functional block pins are listed alphabetically within each of the following pin types 1 inputs and input outputs 2 output pins 3 reference voltages and 4 supply pins UM10208 Chapter 25 LPC2800 pinning Rev 02 1 June 2007 User manual Table 362 Pin descriptions by module Signal name Ball Type 1 Description Analog in dual co...

Page 313: ...PIO pin DAO interface BCKO P3 5 G18 FO DAO bit clock 5 V tolerant GPIO pin DATO P3 6 F17 FO DAO serial data output 5 V tolerant GPIO pin DCLKO P3 3 F16 FO 256 clock output 5 V tolerant GPIO pin WSO F18 O DAO word select 5 V tolerant pin DC to DC converters START L17 I DC to DC activation STOP L18 I DC to DC deactivation DCDC_CLEAN M18 P reference circuit ground not connected to substrate DCDC_GND ...

Page 314: ...GPIO pins A1 P0 17 E17 A2 P0 18 E18 A3 P0 19 D16 A4 P0 20 D17 A5 P0 21 D18 A6 P0 22 A18 A7 P0 23 B18 A8 P0 24 C18 A9 P0 25 B17 A10 P0 26 C17 A11 P0 27 B16 A12 P0 28 C16 A13 P0 29 B15 A14 P0 30 C15 A15 P0 31 A14 FO address bus for static memory GPIO pins A16 P1 0 B14 A17 P1 1 C14 A18 P1 2 A13 A19 P1 3 B13 A20 P1 4 C13 BLS0 P1 12 A12 FO byte lane select for D 7 0 active LOW for static memory GPIO pi...

Page 315: ... P2 3 J16 FI start up MODE PIN2 pull down 5 V tolerant GPIO pin P2 0 K16 FI 5 V tolerant GPIO pin P2 1 K17 FI 5 V tolerant GPIO pin I2C bus interface SCL H16 I O serial clock input open drain output 5 V tolerant pin SDA J17 I O serial data input open drain output 5 V tolerant pin JTAG interface JTAG_SEL U4 I JTAG selection pull down 5 V tolerant pin JTAG_TCK V4 I JTAG reset input pull down 5 V tol...

Page 316: ...put VDD OSC1V8 U9 P 1 8 V VSS OSC T9 P ground Reset RESET T14 I master reset active LOW 5 V tolerant pin UART CTS P6 2 K2 FI clear to send or transmit flow control active LOW 5 V tolerant GPIO pin RXD P6 0 K3 FI serial input 5 V tolerant GPIO pin RTS P6 3 K1 FO request to send or receive flow control active LOW 5 V tolerant GPIO pin TXD P6 1 L3 FO serial output 5 V tolerant GPIO pin USB interface ...

Page 317: ...nal memory controller VDD2 FLASH1V8 V16 P 1 8 V for internal flash memory VDD2 IO3V3 V5 P 3 3 V for peripherals VDD3 IO3V3 V14 P 3 3 V for peripherals VDD4 IO3V3 J18 P 3 3 V for peripherals VDD5 IO3V3 R1 P 3 3 V for peripherals VDD6 IO3V3 R2 P 3 3 V for peripherals VSS1 CORE G1 P ground for internal RAM and ROM VSS1 EMC A15 P ground for external memory controller VSS1 INT T12 P ground for other in...

Page 318: ...0 bit ADC AIN2 U6 input Multiplexed analog input 10 bit ADC AIN3 T6 input Multiplexed analog input 10 bit ADC AIN4 U5 input Multiplexed analog input 10 bit ADC AINL T4 input analog L input channel Dual ADC AINR T1 input analog R input channel Dual ADC AOUTL M2 output DAC L analog out Dual DAC AOUTR M3 output DAC R analog out Dual DAC BLS0 P1 12 A12 func output byte lane select for D 7 0 low active...

Page 319: ... input voltage DC DC DCDC_VDDO 1V8 N18 DC DC2 1 8v output voltage DC DC DCDC_VDDO 3V3 R18 DC DC1 3 3v output voltage DC DC DCDC_VSS1 P18 ground for DC DC1 not connected to substrate DC DC DCDC_VSS2 N16 ground for DC DC2 not connected to substrate DC DC DCDC_VUSB T18 connect to 5V pin of USB connector DC DC DCLKO P3 3 F16 func output 256 fs clock output 5V tolerant GPIO pin DAO DM T17 input output ...

Page 320: ...c input data bus from to MCI SD card input output 5V tolerant GPIO pin MCI SD MD1 P5 4 J2 func input data bus from to MCI SD card input output 5V tolerant GPIO pin MCI SD MD2 P5 3 J1 func input data bus from to MCI SD card input output 5V tolerant GPIO pin MCI SD MD3 P5 2 J3 func input data bus from to MCI SD card input output 5V tolerant GPIO pin MCI SD MODE1 P2 2 K18 func input start up MODE PIN...

Page 321: ...FLASH1V8 V15 1 8V for internal Flash memory Flash VDD1 EMC A16 1 8V or 3 3V for external memory controller EMC VDD1 IO3V3 E1 3 3V for peripherals power gnd VDD1 USB1V8 U15 analog 1 8V USB VDD2 CORE1V8 V11 1 8V for core power gnd VDD2 EMC A7 1 8V or 3 3V for external memory controller EMC VDD2 FLASH1V8 V16 1 8V for internal Flash memory Flash VDD2 IO3V3 V5 3 3V for peripherals power gnd VDD2 USB1V8...

Page 322: ...power gnd VSS3 INT T11 Ground for other internal blocks power gnd VSS3 IO V13 Ground for peripherals power gnd VSS3 USB T16 analog ground USB VSS4 IO H18 Ground for peripherals power gnd VSS5 IO P2 Ground for peripherals power gnd VSS6 IO P1 Ground for peripherals power gnd WE P1 15 C11 func output write enable low active for SDRAM and static memory GPIO pin EMC X32I V7 input 32 768 kHz oscillator...

Page 323: ... P1 3 14 A16 P1 0 15 A13 P0 29 16 A11 P0 27 17 A9 P0 25 18 A7 P0 23 Row C 1 LD1 P4 5 2 LD0 P4 4 3 LD2 P4 6 4 D8 P0 8 5 D9 P0 9 6 D10 P0 10 7 D12 P0 12 8 D14 P0 14 9 STCS0 P1 5 10 CAS P1 16 11 WE P1 15 12 DQM0 P1 10 13 A20 P1 4 14 A17 P1 1 15 A14 P0 30 16 A12 P0 28 17 A10 P0 26 18 A8 P0 24 Row D 1 LD4 P4 8 2 LD3 P4 7 3 LD5 P4 9 4 13 14 15 16 A3 P0 19 17 A4 P0 20 18 A5 P0 21 Row E 1 VDD1 IO3V3 2 LD6...

Page 324: ... 3 i c 1 4 13 14 15 16 RREF 17 DCDC_LX1 18 DCDC_VSS1 Row R 1 VDD5 IO3V3 2 VDD6 IO3V3 3 i c 1 4 13 14 15 16 VSS2 USB 17 VSS1 USB 18 DCDC_VDDO 3V3 Row T 1 AINR 2 i c 1 3 VCOM DADC 4 AINL 5 JTAG_TDI 6 AIN3 7 AIN1 8 X32O 9 VSS OSC 10 XTALI 11 VSS3 INT 12 VSS1 INT 13 JTAG_TRST 14 RESET 15 CONNECT 16 VSS3 USB 17 DM 18 DCDC_VUSB Row U 1 VREF DADC 2 VREFP DADC 3 VDD DADC3V3 4 JTAG_SEL 5 AIN4 6 AIN2 7 AIN0...

Page 325: ...DD2 IO VSS2 IO X32I VSS OSC32 XTALO VDD ADC3 VDD2 CORE VSS2 CORE VSS3 IO VDD3 IO VDD1 FLASH VDD2 FLASH VSS3 CORE VDD4 USB U VREF DADC VREFP DADC VDD DADC3 JTAG SEL AIN4 AIN2 AIN0 VDD OSC32 VDD OSC VSS ADC VSS2 INT JTAG TMS JTAG TDO VBUS VDD1 USB VDD2 USB DP VDD3 USB T AINR i c 1 VCOM DADC AINL JTAG TDI AIN3 AIN1 X32O VSS OSC XTALI VSS3 INT VSS1 INT JTAG TRST RESET CONN ECT VSS3 USB DM DCDC VUSB R ...

Page 326: ... details The figure applies to pins noted below All LCD interface pins LCS P4 0 LRS P4 1 LRW P4 2 LER P4 3 LD0 P4 4 LD1 P4 5 LD2 P4 6 LD3 P4 7 LD4 P4 8 LD5 P4 9 LD6 P4 10 LD7 P4 11 All MCI SD card interface pins MCLK P5 0 MCMD P5 1 MD3 P5 2 MD2 P5 3 MD1 P5 4 MD0 P5 5 All DAI and DAO pins DATI P3 0 BCKI P3 1 WSI P3 2 DCLKO P3 3 BCKO P3 5 DATO P3 6 All UART pins RXD P6 0 TXD P6 1 CTS P6 2 RTS P6 3 O...

Page 327: ... A19 P1 3 A20 P1 4 All external memory control pins except MCLKO P1 14 STCS0 P1 5 STCS1 P1 6 STCS2 P1 7 DYCS P1 8 CKE P1 9 DQM0 P1 10 DQM1 P1 11 BLS0 P1 12 BLS1 P1 13 WE P1 15 CAS P1 16 RAS P1 17 OE P1 18 RPO P1 19 2 5 3 External memory interface clock output This is a non 5V tolerant I O pin The output is faster than the other external memory interface pins with approximately a 4ns rise and fall ...

Page 328: ... 2 5 5 I2C pins These are specialized I2C interface pins They are 5V tolerant have input hysteresis and a slew rate controlled open drain output Figure 25 43 shows the structure of an I2C interface pin Refer to the DC specification section of the device data sheet for voltage and current details The figure applies to the I2C interface pins SCL SDA 2 5 6 Input pins with pull down These pins are 5V ...

Page 329: ...ullup Figure xx shows the structure of a standard input pin with pullup Refer to the DC specification section of the device data sheet for voltage and current details The figure applies to the pins JTAG_TCK JTAG_TMS JTAG_TDI and RESET 2 5 8 Analog input ouput functions These pins provide analog input or output to or from the internal function The pins themselves provide only ESD protection Fig 44 ...

Page 330: ...nductors UM10208 Chapter 25 LPC2800 pinning The figure applies to the pins XTALI XTALO X32I X32O VSS1 INT AIN4 AIN3 AIN2 AIN1 AIN0 AOUTR AOUTL VREFP DAC VREFN DAC AINR AINL CONNECT DP DM RREF START STOP DCDC_LX2 DCDC_LX1 and DCDC_VUSB Fig 46 Analog input or output pins PIN VDD GND analog function ...

Page 331: ... direction control and data register for each port Separate set and clear registers allow controlling only selected pins without side effects on other pins Each GPIO pin is connected to the Event Router and cause an interrupt or wakeup event Interrupt and wakeup functions are asynchronous and operate when clocks are not present Pin state registers allow monitoring the state of all GPIO pins even i...

Page 332: ...IO is shared with the write enable CAS P1 16 This GPIO is shared with the column address strobe RAS P1 17 This GPIO is shared with the row address strobe OE P1 18 This GPIO is shared with the static memory output enable RPO P1 19 This GPIO is shared with the SyncFlash reset power down signal P2 4 pins MODE1 P2 3 to MODE0 P2 2 These GPIOs are shared with the boot mode select inputs P2 1 to P2 0 The...

Page 333: ...O output enable and when enabled the MODE0 register is the GPIO data value See Table 26 367 All of these bit pairs reset to the value 01 so that all potential GPIO pins default to the peripheral function either input or output depending on the default for the that function P5 6 pins MD0 P5 5 to MD3 P5 2 These GPIOs are shared with the SD MCI data bus MCMD P5 1 This GPIO is shared with the SD MCI c...

Page 334: ...s can be read from them R W 0 0x8000 3020 0x8000 3060 0x8000 30A0 0x8000 30E0 0x8000 3120 0x8000 3160 0x8000 31A0 0x8000 31E0 MODE0 0 7 MODE0 Registers All of the m0 bits in a GPIO pin group port can be loaded by writing these registers and the state of the m0 bits can be read from them R W all 1s within used bits 0x8000 3010 0x8000 3050 0x8000 3090 0x8000 30D0 0x8000 3110 0x8000 3150 0x8000 3190 ...

Page 335: ...8 0x8000 3118 0x8000 3158 0x8000 3198 0x8000 31D8 PINS 0 7 Pin State Registers The current state of all the pins in each group port can be read from these registers regardless of whether the pins are configured for GP input GP output or functional I O RO pin state for inputs see module desc for outputs 0x8000 3000 0x8000 3040 0x8000 3080 0x8000 30C0 0x8000 3100 0x8000 3140 0x8000 3180 0x8000 31C0 ...

Page 336: ...NS_1 0x8000 3040 Table 372 Bit Signal correspondence in input group 1 EMC registers Bit 31 30 29 28 27 26 25 24 Signal reserved Bit 23 22 21 20 19 18 17 16 Signal reserved RPO P1 19 OE P1 18 RAS P1 17 CAS P1 16 Bit 15 14 13 12 11 10 9 8 Signal WE P1 15 MCLKO P1 14 BLS1 P1 13 BLS0 P1 12 DQM1 P1 11 DQM0 P1 10 CKE P1 9 DYCS P1 8 Bit 7 6 5 4 3 2 1 0 Signal STCS2 P1 7 STCS1 P1 6 STCS0 P1 5 A20 P1 4 A19...

Page 337: ...l reserved Bit 23 22 21 20 19 18 17 16 Signal reserved Bit 15 14 13 12 11 10 9 8 Signal reserved Bit 7 6 5 4 3 2 1 0 Signal reserved MODE1 P2 3 MODE0 P2 2 P2 1 P2 0 Table 375 Port 3 DAI DAO Registers Register Address MODE1_3 0x8000 30E0 MODE0_3 0x8000 30D0 MODE1S_3 0x8000 30E4 MODE0S_3 0x8000 30D4 MODE1C_3 0x8000 30E8 MODE0C_3 0x8000 30D8 PINS_3 0x8000 30C0 Table 376 Bit Signal correspondence in P...

Page 338: ...MODE1C_4 0x8000 3128 MODE0C_4 0x8000 3118 PINS_4 0x8000 3100 Table 378 Bit Signal correspondence in Port 4 LCD registers Bit 31 30 29 28 27 26 25 24 Signal reserved Bit 23 22 21 20 19 18 17 16 Signal reserved Bit 15 14 13 12 11 10 9 8 Signal reserved LD7 P4 11 LD6 P4 10 LD5 P4 9 LD4 P4 8 Bit 7 6 5 4 3 2 1 0 Signal LD3 P4 7 LD2 P4 6 LD1 P4 5 LD0 P4 4 LER P4 3 LRW P4 2 LRS P4 1 LCS P4 0 Table 379 Po...

Page 339: ...5 24 Signal reserved Bit 23 22 21 20 19 18 17 16 Signal reserved Bit 15 14 13 12 11 10 9 8 Signal reserved Bit 7 6 5 4 3 2 1 0 Signal reserved MD0 P5 5 MD1 P5 4 MD2 P5 3 MD3 P5 2 MCMD P5 1 MCLK P5 0 Table 381 Port 6 UART Registers Register Address MODE1_6 0x8000 31A0 MODE0_6 0x8000 3190 MODE1S_6 0x8000 31A4 MODE0S_6 0x8000 3194 MODE1C_6 0x8000 31A8 MODE0C_6 0x8000 3198 PINS_6 0x8000 3180 Table 382...

Page 340: ...ess MODE1_7 0x8000 31E0 MODE0_7 0x8000 31D0 MODE1S_7 0x8000 31E4 MODE0S_7 0x8000 31D4 MODE1C_7 0x8000 31E8 MODE0C_7 0x8000 31D8 PINS_7 0x8000 31C0 Table 384 Bit Signal correspondence in Port 7 USB registers Bit 31 30 29 28 27 26 25 24 Signal reserved Bit 23 22 21 20 19 18 17 16 Signal reserved Bit 15 14 13 12 11 10 9 8 Signal reserved Bit 7 6 5 4 3 2 1 0 Signal reserved VBUS P7 0 ...

Page 341: ... Advanced Peripheral Bus CISC Complex Instruction Set Computer CGU Clock Generation Unit DAC Digital to Analog Converter DMA Direct Memory Access FIQ Fast Interrupt Request GPIO General Purpose Input Output IrDA Infrared Data Association IRQ Interrupt Request LCD Liquid Crystal Display PLL Phase Locked Loop RISC Reduced Instruction Set Computer SD MMC Secure Digital MultiMedia Card SDRAM Synchrono...

Page 342: ...ument including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where ...

Page 343: ...UM10208_2 NXP B V 2007 All rights reserved User manual Rev 02 1 June 2007 343 of 362 NXP Semiconductors UM10208 Chapter 27 LPC2800 Supplementary information Notes ...

Page 344: ...onverter registers 48 Table 27 DCDC converter 1 Adjustment register DCDCADJUST1 address 0x8000 5004 49 Table 28 Adjustment range for DCDC converter 1 49 Table 29 DCDC converter 2 Adjustment register DCDCADJUST2 address 0x8000 5008 49 Table 30 Adjustment range for DCDC converter 2 49 Table 31 DCDC Clock Select register DCDCCLKSEL address 0x8000 500C 50 Table 32 CGU configuration registers 53 Table ...

Page 345: ...ictWR address 0x8000 8044 99 Table 90 Dynamic Memory Active to Active Command Period Register EMCDynamictRC address 0x8000 8048 99 Table 91 Dynamic Memory Auto refresh Period Register EMCDynamictRFC address 0x8000 804C 100 Table 92 Dynamic Memory Exit Self refresh Register EMCDynamictXSR address 0x8000 8050 100 Table 93 Dynamic Memory Active Bank A to Active Bank B Time Register EMCDynamictRRD add...

Page 346: ...ondence in input group 1 registers 141 Table 145 Registers related to Input Group 2 142 Table 146 Bit Signal correspondence in input group 2 registers 142 Table 147 Registers related to Input Group 3 143 Table 148 Bit Signal correspondence in input group 3 registers 143 Table 149 Event Router Output Register EVOUT 0x8000 0D40 143 Table 150 Features Register EVFEATURES 0x8000 0E00 144 Table 151 Rea...

Page 347: ...r Length Registers DMA 0 7 AltLength 0x8010 3A08 3A78 185 Table 206 Alternate Configuration Registers DMA 0 7 AltConfig 0x8010 3A0C 3A7C 185 Table 207 Global Enable Register DMA_Enable 0x8010 3C00 185 Table 208 Global Status and Clear Register DMA_Stat 0x8010 3C04 186 Table 209 IRQ Mask Register DMA_IRQMask 0x8010 3C08 187 Table 210 DMA Software Interrupt Register DMA_SoftInt 0x8010 3C10 188 Table...

Page 348: ...us Register UDMAStat 0x8004 0408 235 Table 263 USB DMA Channel Status Registers UDMA0Stat 0x8004 0000 UDMA1Stat 0x8004 0040 236 Table 264 USB DMA Interrupt Status Register UDMAIntStat 0x8004 0410 237 Table 265 USB DMA Interrupt Enable Register UDMAIntEn 0x8004 0418 238 Table 266 USB DMA Interrupt Disable Register UDMAIntDis 0x8004 0420 238 Table 267 USB DMA Interrupt Clear Register UDMAIntClr 0x80...

Page 349: ...9 Table 319 SAO2 register map 280 Table 320 SAO2 Status Register SAOSTAT2 0x8020 0290 281 Table 321 SAO2 Mask Register SAOMASK2 0x8020 0294 281 Table 322 SD MCI Card Interface Pin Description 284 Table 323 Command format 288 Table 324 Simple response format 289 Table 325 Long response format 289 Table 326 Command path status flags 289 Table 327 CRC token status 292 Table 328 Data path status flags...

Page 350: ...cription 332 Table 367 m1 0 state vs pin state 333 Table 368 I O configuration register descriptions 334 Table 369 Port 0 EMC registers 335 Table 370 Bit Signal correspondence in Port 0 EMC registers 335 Table 371 Port 1 EMC registers 336 Table 372 Bit Signal correspondence in input group 1 EMC registers 336 Table 373 Port 2 GPIO Registers 336 Table 374 Bit Signal correspondence in Port 2 GPIO reg...

Page 351: ...m of the interrupt controller 119 Fig 19 Watchdog block diagram 135 Fig 20 RTC inputs and outputs 145 Fig 21 Auto RTS functional timing 162 Fig 22 Auto CTS functional timing 163 Fig 23 Autobaud a mode 0 and b mode 1 waveform 167 Fig 24 UART block diagram 176 Fig 25 GPDMA block diagram 178 Fig 26 I2C bus configuration 194 Fig 27 USB device controller block diagram 209 Fig 28 Block diagram of the Du...

Page 352: ...g 1 Introduction 14 2 Features 14 3 Cache definitions 14 4 Description 15 4 1 Cache enabling and function 18 4 1 1 Cache function details 18 5 Register description 18 5 1 Cache Reset Status register CACHE_RST_STAT 0x8010 4000 19 5 2 Cache Settings register CACHE_SETTINGS 0x8010 4004 20 5 3 Cache Page Enable Control register CACHE_PAGE_CTRL 0x8010 4008 21 5 4 Cache Read Misses counter C_RD_MISSES 0...

Page 353: ...ery power to USB power 47 4 DC DC registers 48 4 1 DCDC converter 1 Adjustment register DCDCADJUST1 address 0x8000 5004 49 4 2 DCDC converter 2 Adjustment register DCDCADJUST2 address 0x8000 5008 49 4 3 DCDC Clock Select register DCDCCLKSEL address 0x8000 500C 50 Chapter 7 Clock Generation Unit CGU and power control 1 Features 51 2 Description 51 3 Register descriptions 53 3 1 CGU configuration re...

Page 354: ... Register EMCDynamictRAS 0x8000 8034 97 10 9 Dynamic Memory Self refresh Exit Time Register EMCDynamictSREX 0x8000 8038 97 10 10 Dynamic Memory Last Data Out to Active Time Register EMCDynamictAPR 0x8000 803C 98 10 11 Dynamic Memory Data in to Active Command Time Register EMCDynamictDAL 0x8000 8040 98 10 12 Dynamic Memory Write Recovery Time Register EMCDynamictWR 0x8000 8044 99 10 13 Dynamic Memo...

Page 355: ...rupts 124 6 2 Workaround 125 6 2 1 Solution 1 Test for an IRQ received during a write to disable IRQs 125 6 2 2 Solution 2 Disable IRQs and FIQs using separate writes to the CPSR 125 6 2 3 Solution 3 Re enable FIQs at the beginning of the IRQ handler 126 7 Interrupt controller usage notes 126 Chapter 10 Timer 1 Features 128 2 Description 128 3 Register descriptions 128 3 1 Timer register map 128 3...

Page 356: ...er description 153 3 1 Receiver Buffer Register RBR 0x8010 1000 when DLAB 0 Read Only 155 3 2 Transmit Holding Register THR 0x8010 1000 when DLAB 0 Write Only 155 3 3 Divisor Latch LSB Register DLL 0x8010 1000 when DLAB 1 155 3 4 Divisor Latch MSB Register DLM 0x8010 1004 when DLAB 1 155 3 5 Interrupt Enable Register IER 0x8010 1004 when DLAB 0 156 3 6 Interrupt Identification Register IIR 0x8010 ...

Page 357: ... 3C00 185 4 2 12 Global Status and Clear Register DMA_Stat 0x8010 3C04 186 4 2 13 IRQ Mask Register DMA_IRQMask 0x8010 3C08 187 4 2 14 DMA Software Interrupt Register DMA_SoftInt 0x8010 3C10 188 4 2 15 DMA Channel 3 External Enable Register DMA3EXTEN 0x8000 5040 188 4 2 16 DMA Channel 5 External Enable Register DMA5EXTEN 0x8000 5044 188 5 Interrupt requests 188 6 Scatter Gather 190 6 1 Linked list...

Page 358: ...SB Interrupt Priority Register USBIntP 0x8004 10B4 217 8 11 USB Interrupt Configuration Register USBIntCfg 0x8004 1010 219 8 12 USB Frame Number Register USBFN 0x8004 1074 220 8 13 USB Scratch Register USBScratch 0x8004 1078 220 8 14 USB Unlock Register USBUnlock 0x8004 107C 220 8 15 USB Endpoint Index Register USBEIX 0x8004 102C 221 8 16 USB Endpoint Type Register USBEType 0x8004 1008 221 8 17 US...

Page 359: ... 244 9 6 Sending data to an IN TX endpoint in Interrupt slave mode 244 9 7 Receiving data from an OUT RX endpoint in DMA mode 244 9 8 Sending data to an IN TX endpoint in DMA mode 245 Chapter 18 Analog to Digital Converter ADC 1 Features 246 2 Description 246 3 Pin description 246 4 Register description 247 4 1 A D Control Register ADCCON 0x8000 2420 248 4 2 A D Select Register ADCSEL 0x8000 2424 ...

Page 360: ...egisters 276 4 1 Stream I O Configuration Register SIOCR 0x8020 0384 277 4 2 Dual DAC Control Register DDACCTRL 0x8020 0398 277 4 3 Dual DAC status register DDACSTAT 0x8020 039C Read Only 279 4 4 Dual DAC Settings Register DDACSET 0x8020 03A0 279 5 Streaming Analog Out SAO2 module 280 5 1 SAO2 registers 280 6 Programming the Dual DAC and SAO2 282 6 1 Setting up the Dual DAC and SAO2 282 6 2 Power ...

Page 361: ...pt Clear Register LCDICLR 0x8010 300C 308 4 7 Read Command Register LCDREAD 0x8010 3014 308 4 8 Instruction Byte Register LCDIBYTE 0x8010 3020 308 4 9 Data Byte Register LCDDBYTE 0x8010 3030 309 4 10 Instruction Word Register LCDIWORD 0x8010 3040 309 4 11 Data Word Register LCDDWORD 0x8010 3080 309 5 LCD interface operation 309 5 1 Resetting a Remote Device 309 5 2 Programming the LCD interface cl...

Page 362: ...Document identifier UM10208_2 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information 362 5 1 6 Port 5 MCI SD Registers 338 5 1 7 Port 6 UART Registers 339 5 1 8 Port 7 USB Registers 339 Chapter 27 Supplementary information 1 Abbreviations 341 2 Legal information 342 2 1 Definitions 342 2 2 Disclaimers 342 2...

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