UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
79 of 362
NXP Semiconductors
UM10208
Chapter 7: LPC2800 CGU
interface) is programmed as 5/12 of the SYS base clock by the fractional divider
(SYSFDCR1), i.e. 25 MHz. The LCD_CLK (LCD bus clock for LCD interface) is
programmed as 1/10 of the SYS base clock by the fractional divider (SYSFDCR3), i.e.
6 MHz. The CPU_CLK (main processor clock) is the same as the input clock (SYS base
clock) from the selection stage (SYS), i.e. 60 MHz. Because the CPU_CLK ( main
processor clock ) is higher than ( twice ) the CPU_GCLK ( gated HCLK for processor
registers ), the bit 4 ( ENOUT_EN ) of the power control register ( CPUPCR2 ) for the
CPU_GCLK ( gated HCLK for processor registers ) must be set.
Code example
#include <lpc288x.h>
#define CGU_FSR_MAIN_PLL 0x8
#define CGU_FSR1 0x1
#define CGU_FSR2 0x2
#define CGU_FDCR_FDRUN 0x1
#define CGU_FDCR_FDRES 0x2
#define CGU_FDCR_FDSTRCH 0x4
#define SYSFDCR0_MSUB 0xC0
#define SYSFDCR0_MADD 0x40
#define SYSFDCR1_MSUB 0xB0
#define SYSFDCR1_MADD 0x70
#define SYSFDCR3_MSUB 0xF0
#define SYSFDCR3_MADD 0x90
#define CGU_ESR_FD0 0x1
#define CGU_ESR_FD1 0x3
#define CGU_ESR_FD3 0x7
#define CGU_ESR_FD5 0xB
#define CGU_PCR_ENOUT_EN 0x10
#define CGU_BCR_FDRUN 0x1
/*********************** Main PLL Setup***************************/
LPPDN = 0x00000001; /* Power down the main PLL */
LPFIN = 0x00000001; /* Select main oscillator as PLL's input clock */
LPMSEL = 0x00000004; /* Multiply input clock by (4 + 1) = 5 */
LPPSEL = 0x00000001; /* Make CCO equal to 4 times PLL output */
LPPDN = 0x00000000; /* Power up the main PLL */
while (LPLOCK == 0x00000000) {}; /* Wait for PLL to lock */
/*********************** Selection Stage ***************************/
if (SYSSSR & CGU_FSR1) {
SYSFSR2 = CGU_FSR_MAIN_PLL; /* Select Main PLL as main clock */
SYSSCR = (SYSSCR & 0xC) | CGU_FSR2; /* Enable side 2 */
} else {
SYSFSR1 = CGU_FSR_MAIN_PLL; /* Select Main PLL as main clock */
SYSSCR = (SYSSCR & 0xC) | CGU_FSR1; /* Enable side 1 */
}
/*********************** Programming the Fractional Divider registers ***************************/
/* Setup SYS Fractional Divider #0 for AHB clock */
