UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
71 of 362
NXP Semiconductors
UM10208
Chapter 7: LPC2800 CGU
3.13 Software reset registers
The final stage of the CGU includes flip-flops that generate a synchronized reset signal for
each of the modules that use the clocks generated by the spreading stages. Each of the
synchronized resets is asserted due to a software reset, power-on reset (RESET pin low)
or a watchdog timer reset.
Each of the modules shown in
can be reset if software writes a 0 to bit 0 of the
register with the name and address indicated. These register bits all reset to 1. Unless the
module is not to be used, software will need to write a 1 back to its software reset register
before it can operate again.
Table 69.
ESRs with ESR_SEL fields
ESRs with 3-bit fields
ESRs with 1-bit fields
APB0ESR0
APB1ESR0
APB0ESR1
APB2ESR
APB3ESR0
EVRTESR
MMIOESR0
AHB0ESR0
RTCESR
MCIESR0
MCIESR1
ADCESR0
UARTESR0
FLSHESR0
ADCESR1
FLSHESR1
FLSHESR2
WDTESR
LCDESR0
LCDESR1
IOCESR
DMAESR0
DMAESR1
CGUESR
USBESR0
CPUESR0
SYSCESR
CPUESR1
CPUESR2
RAMESR
ROMESR
EMCESR0
EMCESR1
MMIOESR1
DDACESR1
DDACESR2
DADCESR1
DADCESR2
DAIESR1
DAIESR2
DAOESR1
DAOESR2
DAOESR3
Table 70.
Software reset registers
Name
Address
Module(s) or Submodule
APB0RES
0x8000 4C18
APB0 including CGU, System Config, Event Router, RTC, ADC,
WDT, IOCONF. Do not clear this bit!
APB0RES2
0x8000 4C1C APB0 bridge. Do not clear this bit!
APB1RES
0x8000 4C20
APB1.
APB1RES2
0x8000 4C24
APB1 bridge.
APB2RES
0x8000 4C28
APB2.
APB3RES
0x8000 4C2C APB3.
APB3RES2
0x8000 4C30
APB3 bridge.
MMIORES
0x8000 4C34
Interrupt Controller
AHB0RES
0x8000 4C38
Processor, RAM, ROM, other AHB. Do not clear this bit!
T0RES
0x8000 4C3C Timer 0
T1RES
0x8000 4C40
Timer 1