NXP Semiconductors LPC2880, User Manual

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User manual Rev. 02 — 1 June 2007 105 of 362
NXP Semiconductors
UM10208
Chapter 8: LPC2800 EMC
[1] Extended wait and page mode cannot be selected simultaneously.
10.21 Static Memory Write Enable Delay Registers (EMCStaticWaitWen0-2 -
0x8000 8204,24,44)
The EMCStaticWaitWen0-2 Registers control the delay from chip select to write enable.
These registers should only be modified during system initialization, or when there are no
current or outstanding transactions. This can be ensured by waiting until the EMC is idle,
and then entering low-power or disabled mode. These registers are accessed with one
wait state.
Table 8–99 shows the EMCStaticWaitWen0-2 Registers.
7 BLS state for
reads If this bit is zero, as it is after a power-on reset, the BLSn[1:0]
outputs are high during reads. This signalling is appropriate for
byte-wide static memories that have their WE input connected to
BLSn[1:0] from the EMC. In this case the BLSn[1:0] outputs must
be high for reads, to prevent writing.
Write a 1 to this bit to indicate that BLSn[1:0] should be both be
low for reads. This signalling is appropriate for 16 bit wide static
memory devices that have BLSn[1:0] connected to their UBn and
LBn (upper byte and lower byte) inputs. In this case, for reads
both UBn and LBn should be asserted low so that the memory
drives both lanes of the bus.
Regardless of this bit, for write operations one or both of
BLSn[1:0] go low to indicate which byte(s) should be written.
0
8 Extended Wait If this bit is zero, as it is after a power-on reset, the
EMCStaticWaitRd and EMCStaticWaitWr Registers control the
length of read and write cycles respectively. Write a 1 to this bit to
select the EMCStaticExtendedWait Register to determine the
length of both read and write cycle. This enables much longer
transactions.
[1]
0
18:9 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. -
19 Write buffer
enable If this bit is zero, as it is after a power-on reset, write buffers are
disabled for the associated memory area. Write a 1 to this bit to
enable the write buffers, which allows higher performance. 0
20 Write Protect If this bit is zero, as it is after a power-on reset, the associated
memory area can be written. Write a 1 to this bit to write-protect
the area. 0
31:21 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. -
Table 98. Static Memory Configuration Registers (EMCStaticConfig0-2 - addresses
0x8000 8200, 0x8000 8220, 0x8000 8240)
Bit Symbol Description POR
Reset
Value