NXP Semiconductors LPC2880, User Manual

Page: 106 / 362

UM10208_2 © NXP B.V. 2007. All rights reserved.
User manual Rev. 02 — 1 June 2007 106 of 362
NXP Semiconductors
UM10208
Chapter 8: LPC2800 EMC
10.22 Static Memory Output Enable Delay Registers (EMCStaticWaitOen0-2
- 0x8000 8208,28,48)
The EMCStaticWaitOen0-2 Registers control the delay from the chip select assertion or
address change, whichever is later, to output enable assertion. These registers should
only be modified during system initialization, or when there are no current or outstanding
transactions. This can be ensured by waiting until the EMC is idle, and then entering
low-power or disabled mode. These registers are accessed with one wait state.
Table 8–100 shows the EMCStaticWaitOen0-2 Registers.
10.23 Static Memory Read Delay Registers (EMCStaticWaitRd0-2 -
0x8000 820C,2C,4C)
The EMCStaticWaitRd0-2 Registers control how long the EMC waits after it asserts the
chip select in a read operation, to when it samples the read data. These registers should
only be modified during system initialization, or when there are no current or outstanding
transactions. This can be ensured by waiting until the EMC is idle, and then entering
low-power or disabled mode. This register is not used if the Extended Wait bit in the
EMCStaticConfig0-2Register is 1. These registers are accessed with one wait state.
Table 8–101 shows the EMCStaticWaitRd0-2 Registers.
Table 99. Static Memory Write Enable Delay registers (EMCStaticWaitWen0-2 - addresses
0x8000 8204, 0x8000 8224, 0x8000 8244)
Bit Symbol Description POR Reset
Value
3:0 WAITWEN Controls the delay from chip select assertion to write enable
assertion, in AHB HCLK clock cycles. The delay is
(W 1)
×
t
HCLK
.
0
31:4 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. -
Table 100. Static Memory Output Enable Delay Registers (EMCStaticWaitOen0-2 - addresses
0x8000 8208, 0x8000 8228, 0x8000 8248)
Bit Symbol Description POR Reset
Value
3:0 WAITOEN Controls the delay from chip select assertion to output
enable assertion, in AHB HCLK cycles. The delay is
(WAITOEN
×
t
HCLK
). Write a non-zero value to reduce power
consumption by memories that can’t return data fast enough
for zero-wait-state operation.
0x0
31:4 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. -