Intel PCH-LP, Programming Manual

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Intel Confidential 6
A.22 PCHSTRP20—Strap 20 Record (Flash Descriptor Records)........................................89
A.23 CPUSTRP0—Strap 0 Record (Flash Descriptor Records) ...........................................90
Figures
3-1 SPI Timing .........................................................................................................20
3-2 PCH Test Load ....................................................................................................21
4-1 Flash Descriptor (Broadwell PCH-LP)......................................................................23
5-1 SFDP Read Instruction Sequence...........................................................................41
7-1 Firmware Image Components ...............................................................................51
7-2 Editable Flash Image Region List ...........................................................................53
7-3 Descriptor Region – Descriptor Map Options ...........................................................53
7-4 Descriptor Region – Fast Read Support Options.......................................................54
7-5 Descriptor Region - Component Section Options......................................................54
7-6 Region Access Control .........................................................................................55
7-7 Descriptor Region – Master Access Section Options..................................................55
7-8 Add New VSCC Table Entry ..................................................................................56
7-9 Add VSCC Table Entry .........................................................................................56
7-10 VSCC Table Entry................................................................................................57
7-11 Remove VSCC Table Entry....................................................................................57
Tables
1-1 Terminology .......................................................................................................10
1-2 Reference Documents ..........................................................................................10
2-1 Region Size vs. Erase Granularity of Flash Components ............................................13
3-1 SPI Timings (20 MHz) ..........................................................................................19
3-2 SPI Timings (33 MHz) ..........................................................................................19
3-3 SPI Timings (50 MHz) ..........................................................................................20
4-1 Region Access Control Table Options......................................................................36
4-2 Recommended Read/Write Settings for Platforms Using Intel® ME Firmware...............37
4-3 Recommended Read/Write Settings for Platforms Using Intel® ME Firmware (Cont’d) ..37
4-4 Jidn - JEDEC ID Portion of Intel® ME VSCC Table ....................................................38
4-5 Vsccn – Vendor-Specific Component Capabilities Portion of the Broadwell PCH-LP Platforms
39
6-1 Recommended Opcodes for FPT Operation ..............................................................45
6-2 Recommended Opcodes for FPT Operation ..............................................................45
6-3 VSCC0 - Vendor-Specific Component Capabilities Register for SPI Component 0 ..........46
6-4 VSCC1 - Vendor Specific Component Capabilities Register for SPI Component 1...........48
6-5 Description of How WSR and WEWS is Used............................................................49