Intel PCH-LP, Programming Manual

Page: 44 / 90

44 523462
Intel Confidential
Configuring BIOS/GbE for SPI Flash Access
6.2 Locking SPI Flash via Status Register
Flash vendors that implement their status register with non-volatile memory can be
updated a limited number of times. This means that this register may wear out before
the desired endurance for the rest of the flash. It is highly recommended that BIOS
vendors and customers do NOT use the SPI flash’s status register to protect the flash in
multiple master systems.
BIOS should try to minimize the number of times that the system is locked and
unlocked.
Care should be taken when using status register based SPI flash protection in multiple
master systems such as Intel
®
ME FW and/or integrated GbE. BIOS must ensure that
any flash based protection will apply to BIOS region only. It should not affect the ME or
GbE regions.
Please contact your desired flash vendor to see if their status register protection bits
volatile or non-volatile. Flash parts implemented with volatile systems do not have this
concern.
6.3 SPI Protected Range Register Recommendations
The PCH has a mechanism to set up to 5 address ranges from HOST access. These are
defined in PR0, PR1, PR2, PR3 and PR4 in the PCH EDS. These address ranges are NOT
unlocked by assertion of Flash descriptor Override.
It is strongly recommended to use a protected range register to lock down the factory
default portion of Intel
®
ME Ignition FW region. The runtime portion should be left
unprotected as to allow BIOS to update it.
It is strongly recommended that if Flash Descriptor Override strap (which can be
checked by reading
FDOPSS (0b Flash Descriptor override is set, 1b not set) in PCH
memory space (4h bit 13))
is set, do not set a Protected range to cover the
Intel
®
ME Ignition FW factory defaults. This would allow a flashing of a complete image
when the Flash descriptor Override strap is set.
6.4 Software Sequencing Opcode Recommendations
It is strongly recommended that the “9Fh” JEDEC ID be used instead of “90h” or “AB”.
The JEDEC ID Council ensures that every SPI flash model is unique. There are flash
vendors that have flash parts of different sizes that report out the same value using the
“90h” opcode.
Intel utilities such as the Flash Programming Tool will incorrectly detect the flash part in
the system and it may lead to undesired program operation.
The Flash Programming Tool requires the following software sequencing opcodes to be
programmed in the OPMENU and corresponding OPTYPE register.
It is strongly recommended that you do not program opcodes write enable commands
into the OPMENU definition. These should be programmed in the PREOP register.
Order of the opcodes is not important, but the OPMENU and OPTYPE do have to
correspond. see OPTYPE— Opcode Type Configuration Register OPMENU-
Opcode Menu Configuration Register in the Broadwell PCH-LP Family External
Design Specification (EDS).