Intel PCH-LP, Programming Manual

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Configuring BIOS/GbE for SPI Flash Access
Erase Opcode (EO) and Block/Sector Erase Size (BSES) should be set based on
the flash part and the firmware on the platform.
• Either Write Status Required (WSR) or
Write Enable on Write Status
(
WEWS
)
should be set on flash devices that require an opcode to enable a write to
the status register. BIOS and GbE will write a 00h to the SPI flash’s status register
to unlock the flash part for every erase/write operation. If this bit is set on a flash
part that has non-volatile bits in the status register then it may lead to pre-mature
wear out of the flash and may result in undesired flash operation. Please refer to
Table 6-5 for a description of how these bits is set and what is the expected
operation from the controller during erase/write operation.
3
Write Status Required (WSR) — RW:
‘0’ = No automatic write of 00h will be made to the SPI flash’s status register
‘1’ = A write of 00h to the SPI flash’s status register will be sent on EVERY write and erase to the
SPI flash performed by Host and GbE.
This register is locked by the Vendor Component Lock (VCL) bit.
Note: Please refer to Table 6-5 for a description of how these bits is used.
3.
2
Write Granularity (WG) — RW:
0: 1 Byte
1: 64 Byte
This register is locked by the Vendor Component Lock (VCL) bit.
If more than one Flash component exists, this field must be set to the lowest common write
granularity of the different Flash components.
If using 64 B write, BIOS must ensure that multiple byte writes do not occur over 256 B
boundaries. This will lead to corruption as the write will wrap around the page boundary on the SPI
flash part. This is a feature in page writeable SPI flash.
1:0
Block/Sector Erase Size (BES)— RW: This field identifies the erasable sector size for all Flash
components.
Valid Bit Settings:
00: 256 Byte
01: 4 KByte
10: 8 KByte
11: 64 K
This register is locked by the Vendor Component Lock (VCL) bit.
Hardware takes no action based on the value of this register. The contents of this register are to be
used only by software and can be read in the HSFSTS.BERASE register in both the BIOS and the
GbE program registers if FLA is less than FPBA .
Table 6-4. VSCC1 - Vendor Specific Component Capabilities Register for SPI Component 1
(Sheet 2 of 2)
Bit Description
Table 6-5. Description of How WSR and WEWS is Used
WSR WEWS Flash Operation
1b 0b
If the Enable Write Status Register opcode (50h) is needed to unlock the status
register. Opcodes sequence sent to SPI flash will bit 50h 01h 00h.
1b 1b
If write enable (06h) will unlock the status register. Opcodes sequence sent to
SPI flash will bit 06h 01h 00h.
0b 0 or 1b
Sequence of 60h is sent to unlock the SPI flash on EVERY write and erase that
Processor or Intel GbE FW performs.