Intel PCH-LP, Programming Manual

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Intel Confidential
APPENDIX A - Descriptor Configuration
A.2 PCHSTRP0—Strap 0 Record (Flash Descriptor
Records)
Flash Address:
FPSBA
+ 000h Size: 32 bits
Default Flash Address: 100h
Bits Description Usage
31:29 Top Swap Block size (TSBS):
000: 64 KB. Invert A16 if Top Swap is enabled (Default)
001: 128 KB. Invert A17 if Top Swap is enabled
010: 256 KB. Invert A18 if Top Swap is enabled
011: 512 KB. Invert A19 if Top Swap is enabled
100: 1 MB. Invert A20 if Top Swap is enabled
101 - 111: Reserved
Notes:
1. This setting is dependent on BIOS architecture and can
be different per design. The BIOS developer for the
target platform has to determine this value.
2. If FWH is set as Boot BIOS destination then PCH only
supports 64 KB Top Swap block size. This value has to
be determined by how BIOS implements Boot-Block.
3. Client supports boot block size of up to 256 KB. Top
Swap block sizes of greater than 256KB are not
supported.
This allows for the system to use alternate code in
order to boot a platform based upon the Top Swap
(GPIO66/SDIO_D0 pulled low during the rising edge
of PWROK.) strap being asserted.
Top Swap inverts an address on access to SPI and
firmware hub, so the processor fetches the alternate
Top Swap block instead of the original boot-block. The
size of the Top Swap block and setting of this field
must be determined by the BIOS developer. If this is
not set correctly, then BIOS boot-block recovery
mechanism will not work.
Note: This setting is not the same for all designs, is
dependent on the architecture of BIOS. The
setting of this field must be determined by
the BIOS developer.
28:25 Reserved, set to ’0’
24
DMI RequesterID Check Disable (DMI_REQID_DIS):
The primary purpose of this strap is to support
environments with multiple processors that each have a
different RequesterID that can each access to Serial Flash.
0 = DMI RequesterID Checks are enabled
1 = DMI RequesterID Checks are disabled. No Requester ID
checking is done on accesses from DMI.
This bit is only applicable for platforms that contain
multiple processor sockets. If multiple processors
need to access Serial Flash then this bit would need to
set to ’1’.
Platforms that have a single processor socket set to
’0’
23:22 Reserved, set to ’0’
21 MACsec Disable (MACSEC_DIS)
0 = MACsec is Enabled
1 = MACsec is Disabled
Notes:
1. If not using Intel integrated wired LAN or if disabling it,
then set to '1'
2. If using Intel integrated wired LAN solution AND the
use of MACsec is desired set to ’0’.
MACsec is a hop-by-hop network security solution. It
provides Layer 2 encryption and authenticity/integrity
protection for packets traveling between MACsec-
enabled nodes of the network. The key components
that need to support this functionality are the server,
client and switch network interface devices.
If not using Intel’s integrated wired solution, then this
field must be set to ’1’.
Note: This setting is not the same for all designs, is
dependent on the board design. The platform
hardware designer can determine the setting
for this
20
LAN PHY Power Control GPIO12 Select
(LANPHYPC_GP12_SEL):
0 = GPIO12 is used in native mode as LANPHYPC
1 = GPIO12 default is General Purpose (GP) output
Notes:
1. If not using Intel integrated wired LAN or if disabling it,
then set to '1'
2. If using Intel integrated wired LAN solution AND if
GPIO12 is routed to LAN_DISABLE_N on the Intel PHY,
this bit should be set to ’0’.
If using Intel integrated wired LAN solution AND if
GPIO12 is routed to LAN_DISABLE_N on the Intel
PHY, this bit must be set to ’0’.
If GPIO12 is routed not routed to LAN_DISABLE_N on
the Intel PHY, this bit must be set to ’1’.
If not using Intel integrated wired LAN or if disabling
it, this bit must be set to '1'
Note: This setting is not the same for all designs, is
dependent on the board design. The platform
hardware designer can determine the setting
for this.