Intel PCH-LP, Programming Manual

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APPENDIX A - Descriptor Configuration
A.5 PCHSTRP3—Strap 3 Record (Flash Descriptor
Records)
Flash Address: FPSBA
+ 00Ch
Default Value: 00000000h
Size: 32 bits
Default Flash Address: 10Ch
A.6 PCHSTRP4—Strap 4 Record (Flash Descriptor
Records)
Flash Address: FPSBA + 010h Size:32 bits
Default Flash Address: 110h
Bits Description Usage
31:0 Reserved, set to ’0’
Bits Description Usage
31:24 Reserved, set to ’0’
23:17
GbE PHY SMBus Address:
This is the 7 bit SMBus address the PHY uses to accept
SMBus cycles from the MAC.
Note: This field must be programmed to 64h.
This is the Intel PHY’s SMBus address.
This field must be programmed to 64h.
GbE PHY SMBus Address and GbE MAC address have
to be programmed to 64h and 70h in order to ensure
proper arbitration of SMBus communication between
the Intel integrated MAC and PHY.
16 Reserved, set to ’0’
15:9
GbE MAC SMBus Address:
This is the 7 bit SMBus address uses to accept SMBus cycles
from the PHY.
Note: This field must be programmed to 70h.
This is the Intel integrated wired MAC’s SMBus
address.
This field must be programmed to 70h.
GbE PHY SMBus Address and GbE MAC address have
to be programmed to 64h and 70h in order to ensure
proper arbitration of SMBus communication between
the Intel integrated MAC and PHY.