Intel PCH-LP, Programming Manual

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APPENDIX A - Descriptor Configuration
A.3 PCHSTRP1—Strap 1 Record (Flash Descriptor
Records)
Flash Address: FPSBA + 004h Default Value: 0000000Fh Size:
32 bits
Default Flash Address: 104h
Bits Description Usage
31:28 Reserved, set to ’0’
27:26 SPI TPM Clock Frequency (STCF)
00: 20 MHz
01: 33 MHz (Default)
All other settings is reserved. This field identifies the frequency that should be used
with the TPM on SPI. This field is undefined if the TPM
on SPI is disabled by softstrap
25 TPM on SPI (TOS)
‘0’ : TPM is not on SPI (Default)
‘1’: TPM is on SPI
24:9 Reserved, set to ‘0’.
8 Chipset configuration, set to ‘1’
7 Dual Output Read Enable (DORE):
‘0’: Dual Output Read is disabled
‘1’: Dual Output Read is enabled (Default) This soft strap only has effect if Dual Output read is
discovered as supported via the SFDP
If parameter table is not detected via SFDP, this bit
has no effect and Dual Output Read is controlled via
the Flash Descriptor Component Section. Dual Output
Fast Read Support Bit
6 Dual I/O Read Enable (DIORE)
‘0’: Dual I/O Read is disabled
‘1’: Dual I/O Read is enabled (Default) this soft strap only has effect if Dual I/O Read is
discovered as supported via the SFDP
5 Quad Output Read Enable (QORE):
‘0’: Quad Output Read is disabled
‘1’: Quad Output Read is enabled (Default) This soft strap only has effect if Quad Output Read is
discovered as supported via the SFDP
4 Quad I/O Read Enable (QIORE):
‘0’: Quad I/O Read is disabled
‘1’: Quad I/O Read is enabled (Default) This soft strap only has effect if Quad Output Read is
discovered as supported via the SFDP
3:0 Chipset configuration, set to ‘1111b’