Intel PCH-LP, Programming Manual

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APPENDIX A - Descriptor Configuration
10:8
GBE PCIe* Port Select (GBE_PCIEPORTSEL)
This strap defines the GbE port.
000: Port 3
001: Port 4
010: Port 5 Lane 0
011: Port 5 Lane 1
100: Port 5 Lane 2
101: Port 5 Lane 3
110-111: Reserved
This field tells the PCH which PCI Express* port an
Intel PHY is connected.
If PHY_PCIE_EN is =’0’, then this field is ignored.
Note: This setting is not the same for all designs, is
dependent on the board design. The platform
hardware designer or schematic review can
determine what PCIe Port the Intel wired PHY
is routed.
7 Chipset configuration. set to’1’b
6 Reserved, set to ’0’
5
PCIe Lane Reversal 2 (PCIELR2)
This bit lane reversal behavior for PCIe Port 5 if configured
as a x4 PCIe port.
0 = PCIe Lanes 0-3 are not reversed.
1 = PCIe Lanes 0-3 are reversed when Port 5 is configured
as a 1x4.
Note: This field only is in effect if PCIEPCS2 is set to '11'b.
If configuring PCIe port 5 as a x4 PCIe bus, reversing
the lanes of this port is done via this strap.
PCI Express port lane reversal can be done to aid in
the laying out of the board.
Note: This setting is dependent on the board
design. The platform hardware designer must
determine if this port needs lane reversal.
4
PCIe Lane Reversal 1 (PCIELR1)
This bit lane reversal behavior for PCIe Port 1 if configured
as a x4 PCIe port.
0 = PCIe Lanes 0-3 are not reversed.
1 = PCIe Lanes 0-3 are reversed when Port 1 is configured
as a 1x4.
Note: This field only is in effect if PCIEPCS1 is set to '11'b.
If configuring PCIe port 1 as a x4 PCIe bus, reversing
the lanes of this port is done via this strap.
PCI Express* port lane reversal can be done to aid in
the laying out of the board.
Note: This setting is dependent on the board
design. The platform hardware designer
can determine if this port needs lane reversal
3:2
Reserved, set to ’0’
1:0
PCI Express Port Configuration Strap 1 (PCIEPCS1).
Straps to set the default value of the PCI Express Port
Configuration 1 register covering PCIe ports 1-4.
11: 1x4 Port 1 (x4), Ports 2-4 (disabled)
10: 2x2 Port 1 (x2), Port 3 (x2), Port 2 and Port 4 (disabled)
01: 1x2, 2x1 Port 1 (x2), Port 2 (disabled), Ports 3 and Port
4 (x1)
00: 4x1 Port 1 (x1), Port 2 (x1), Port 3 (x1) and Port 4 (x1)
Note: Refer to EDS for PCIe supported port
configurations.
Setting of this field depend on what PCIe ports 1-4
configurations are desired by the board manufacturer.
Only the x4 configuration ("11") has the option of
lane reversal if PCIELR1 is set to ’1’.
Note: This field must be determined by the PCI
Express port requirements of the design. The
platform hardware designer must determine
this setting.
Bits Description Usage