Intel PCH-LP, Programming Manual

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Configuring BIOS/GbE for SPI Flash Access
6.5 Recommendations for Flash Configuration
Lockdown and Vendor Component Lock Bits
6.5.1 Flash Configuration Lockdown
It is strongly recommended that BIOS sets the Host and GbE Flash Configuration
Lock-Down (FLOCKDN) bits (located at 04h and MBAR +04h respectively)
to ‘1’ on production platforms. If these bits are not set, it is possible to make register
changes that can cause undesired host, integrated GbE and Intel
®
ME functionality as
well as lead to unauthorized flash region access.
Refer to HSFS— Hardware Sequencing Flash Status Register in the Serial
Peripheral Interface Memory Mapped Configuration Registers section and
HSFS— Hardware Sequencing Flash Status Register in the GbE SPI Flash
Programing Registers section in the Broadwell PCH-LP Family External Design
Specification (EDS).
6.5.2 Vendor Component Lock
It is strongly recommended that BIOS sets the Vendor Component Lock (VCL) bits.
These bits are located in the BIOS/GbE VSCC0 registers. VCL applies the lock to both
VSCC0 and VSCC1 even if VSCC1 is not used. Without the VCL bits set, it is possible to
make Host/GbE VSCC register(s) changes in that can cause undesired host and
integrated GbE SPI flash functionality.
Refer to VSCC— Vendor Specific Component Capabilities Register in the
Broadwell PCH-LP Family External Design Specification (EDS) for more information.
6.6 Host Vendor Specific Component Control
Registers (VSCC)
VSCC are memory mapped registers are used by the PCH when BIOS or Integrate LAN
reads, programs or erases the SPI flash via Hardware sequencing.
Flash Partition Boundary Address (FBPBA) has been removed and UVSCC and LVSCC
has been replaced with VSCC0 and VSCC1 in Broadwell PCH-LP. VSCC0 is for SPI
component 0 and VSCC1 is for SPI component 1. SPI controller will determine which
VSCC (VCSCC0 or VCSCC1) to be used by comparing Flash Linear Address (FLA) with
Table 6-1. Recommended Opcodes for FPT Operation
Function OPMENU OPTYPE
Read Data 0x03 ‘10’
Read Status 0x05 ‘00’
Read SFDP 0x5A ‘10’
JEDEC ID 0x9F ‘00’
64kB Erase 0xD8 ‘11’
Table 6-2. Recommended Opcodes for FPT Operation
Function PREOP
Write Enable 0x06