Intel PCH-LP, Programming Manual

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Intel Confidential
PCH SPI Flash Compatibility Requirement
3 PCH SPI Flash Compatibility
Requirement
3.1
Intel
®
microarchitecture code name Broadwell
PCH-LP SPI Flash Requirements
• Broadwell PCH-LP Family allows for up to two SPI flash devices to store BIOS,
Intel
®
ME FW and security keys for Platform Data Region and integrated LAN
information.
— Intel
®
ME FW is required for Broadwell PCH-LP Family-based
platforms!
— Each SPI component can support up to 64 MB (128 MB total addressable) using
26-bit addressing
• 3.3V SPI I/O buffer VCC
• SPI Fast Read instruction is supported and frequency of 20 MHz, 33 MHz and 50
MHz
— 50 MHz support requires component that meet 66Mhz timing
• SPI Dual Output and Dual I/O Fast Read instruction is supported with frequency of
20 MHz, 33M hz and 50 MHz
• SPI Quad Output and Quad I/O Fast read instruction is supported with frequency of
20 MHz, 33 MHz and 50 MHz
If there are two SPI components, both components have to support fast read in order
to enable Fast Read in PCH.
3.1.1 SPI-based BIOS Requirements
• Erase size capability of: 4 KBytes.
• Serial flash device must ignore the upper address bits such that an address of
FFFFFFh aliases to the top of the flash memory.
• SPI Compatible Mode 0 support: Clock phase is 0 and data is latched on the rising
edge of the clock.
• If the device receives a command that is not supported or incomplete (less than 8
bits), the device must discard the cycle gracefully without any impact on the flash
content.
• An erase command (page, sector, block, chip, etc.) must set all bits inside the
designated area (page, sector, block, chip, etc.) to 1 (Fh).
• Status Register bit 0 must be set to 1 when a write, erase or write to status register
is in progress and cleared to 0 when a write or erase is NOT in progress.
• Devices requiring the Write Enable command must automatically clear the Write
Enable Latch at the end of Data Program instructions.
• Byte write must be supported. The flexibility to perform a write between 1 byte to
64 bytes is recommended.
• SPI flash parts that do not meet Hardware sequencing command set requirements
may work in BIOS only platforms via software sequencing.