Intel PCH-LP, Programming Manual

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Intel Confidential
PCH SPI Flash Compatibility Requirement
3.1.4 SFDP
Serial flash with SFDP have their supported capabilities and commands stored inside
the serial flash devices. The controller will discover the attributes needed to operate.
Please refer to JEDEC standard Serial Flash Discoverable Parameters in Standard
JESD216, for detail instruction and guideline. the document is available on the JEDEC
Website www.jedec.org.
3.1.5 JEDEC ID (Opcode 9Fh)
Since each serial flash device may have unique capabilities and commands, the JEDEC
ID is the necessary mechanism for identifying the device so the uniqueness of the
device can be comprehended by the controller (master). The JEDEC ID uses the opcode
9Fh and a specified implementation and usage model. This JEDEC Standard
Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV1
and is available on the JEDEC website: www.jedec.org.
3.1.6 Multiple Page Write Usage Model
Intel platforms have firmware usage models require that the serial flash device support
multiple writes to a page (minimum of 512 writes) without requiring a preceding erase
command. BIOS commonly uses capabilities such as counters that are used for error
logging and system boot progress logging. These counters are typically implemented
by using byte-writes to ‘increment’ the bits within a page that have been designated as
the counter. The Intel firmware usage models require the capability for multiple data
updates within any given page. These data updates occur via byte-writes without
executing a preceding erase to the given page. Both the BIOS and Intel Management
Engine firmware multiple page write usage models apply to sequential and non-
sequential data writes.
Flash parts must also support the writing of a single bytes 1024 times in a single 256
Byte page without erase. There will be 64 pages where this usage model will occur.
These 64 pages will be every 16 Kilo bytes.