Intel PCH-LP, Programming Manual

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Configuring BIOS/GbE for SPI Flash Access
4
Write Enable on Write Status (WEWS) — RW:
‘0’ = 50h will be the opcode used to unlock the status register on the SPI flash if WSR (bit 3) is set
to 1b.
‘1’ = 06h will be the opcode used to unlock the status register on the SPI flash if WSR (bit 3) is set
to 1b.
This register is locked by the Vendor Component Lock (VCL) bit.
Note: Please refer to Table 6-5 for a description of how these bits is used.
7.
3
Write Status Required (WSR) — RW:
‘0’ = No automatic write of 00h will be made to the SPI flash’s status register.
‘1’ = A write of 00h to the SPI flash’s status register will be sent on EVERY write and erase to the
SPI flash performed by Host and GbE.
This register is locked by the Vendor Component Lock (VCL) bit.
Note: Please refer to Table 6-5 for a description of how these bits is used.
8.
2
Write Granularity (WG) — RW:
0: 1 Byte
1: 64 Byte
This register is locked by the Vendor Component Lock (VCL) bit.
Notes:
1.If more than one Flash component exists, this field must be set to the lowest common write
granularity of the different Flash components
2.If using 64 B write, BIOS must ensure that multiple byte writes do not occur over 256 B
boundaries. This will lead to corruption as the write will wrap around the page boundary on
the SPI flash part. This is a feature in page writable SPI flash.
1:0
Block/Sector Erase Size (BES)— RW:
This field identifies the erasable sector size for Flash components.
Valid Bit Settings:
00: 256 Byte
01: 4 KByte
10: 8 KByte
11: 64 K
This register is locked by the Vendor Component Lock (VCL) bit.
Hardware takes no action based on the value of this register. The contents of this register are to be
used only by software and can be read in the HSFSTS.BERASE register in both the BIOS and the
GbE program registers if FLA is less than FPBA .
Table 6-3. VSCC0 - Vendor-Specific Component Capabilities Register for SPI Component
0 (Sheet 2 of 2)
Bit Description