Intel PCH-LP, Programming Manual

Page: 12 / 90

12 523462
Intel Confidential
PCH SPI Flash Architecture
which is having CPPT set to 1. CPPT is located at VSCC0 (for SPI 0) and VSCC1 (for SPI
1). Next, the SPI controller will look for a descriptor signature on the SPI flash device
on Chip Select 0 at address 0x10. If the signature is present and valid, then the PCH
controller will boot in Descriptor mode. It will load up the descriptor into corresponding
registers in the PCH. If the signature is NOT present the PCH will boot in non descriptor
mode where integrated LAN and all Intel Management Engine Firmware will be
disabled. Even if the PCH boot in non descriptor mode, SFDP parameters are available
for software use. Whether there is a valid descriptor or not, the PCH will look to the
BIOS boot straps to determine the location of BIOS for host boot.
See Boot BIOS strap in the Functional Straps of the latest Intel I/O Controller Hub
Family External Design Specification (EDS) for Broadwell PCH-LP Family for more
detailed information.
If LPC is chosen as the BIOS boot destination, then the PCH will fetch the reset vector
on top of the firmware hub flash device.
If SPI is chosen as the BIOS destination, it will either fetch the reset vector on top of
the SPI flash device on chip select 0, or if the PCH is in descriptor mode it will
determine the location of BIOS through the base address that is defined in the SPI flash
descriptor.
See
113H287H
Chapter 4, “Descriptor Overview” and for more detailed information.
2.6 Flash Regions
Flash Regions only exist in Descriptor mode. The controller can divide the SPI flash in
up to five separate regions.
The descriptor (Region 0) must be located in the first sector of component 0 (offset
0x10). Descriptor and Intel ME regions are required for all Broadwell PCH-LP Family
based platforms.
If Regions 0, 2, 3 or 4 are defined they must be on SPI. BIOS can be on either FWH or
SPI. The BIOS that will load on boot will be set by Boot BIOS destination straps.
Only three masters can access the five regions: Host CPU, integrated LAN, and
Intel ME.
2.6.1 Flash Region Sizes
SPI flash space requirements differ by platform and configuration. Please refer to
documentation specific to your platform for BIOS and ME Region flash size estimates.
The Flash Descriptor requires one block. GbE requires two separate blocks. The amount
of actual flash space consumed for the above regions are dependent on the erase
granularity of the flash part. Assuming 2 Mbyte BIOS, 64 Mb flash part is the target size
of flash for largest configuration. BIOS size will determine how small of a flash part can
be used for the platform.
Region Content
0 Descriptor
1 BIOS
2
ME – Intel
®
Management Engine Firmware (Intel
®
ME FW)
3 GbE – Location for Integrated LAN firmware and MAC address
4 PDR – Platform Data Region