Intel PCH-LP, Programming Manual

Page: 50 / 90

50 523462
Intel Confidential
Configuring BIOS/GbE for SPI Flash Access
Note: WSR or WEWS should be not be set on devices that use non volatile memory
for their status register. Setting this bit will cause operations to be ignored, which
may cause undesired operation. Ask target flash vendor if this is the case for the target
flash. See
356H
6.1 Unlocking SPI Flash Device Protection for Broadwell PCH-LP Platform and
358H
6.2 Locking SPI Flash via Status Register for more information.
Write Granularity (WG) bit should be set based on the capabilities of the flash
device. If the flash part is capable of writing 1 to 64 bytes (or more) with the 02h
command you can set this bit 0 or 1. Setting this bit high will result in faster write
performance. If flash part only supports single byte write only, then set this bit to 0.
Setting this bit high requires that BIOS ensure that no multiple byte write operation
does not cross a 256 Byte page boundary, as it will have unintended results. This is a
feature of page programming capable flash parts.
Vendor Component Lock (VCL) should remain unlocked during development, but
locked in shipping platforms. When VCL and FLOCKDN are set, it is possible that you
may not be able to use in system programming methodologies including Intel Flash
Programming Tool if programmed improperly. It will require a system reset to unlock
this register and BIOS not to set this bits. See
354H
6.5 Recommendations for Flash
Configuration Lockdown and Vendor Component Lock Bits for more details.
All reserved bits should set to zeros.
6.7 Host VSCC Register Settings
To understand general guidelines for VSCC settings with different SPI flash devices,
please refer to VSCCommn.bin content application note (VSCCommn_bin
Content.pdf under Flash Image Tool directory). VSCCommn.bin contains SPI devices
vendor ID, device ID and recommended VSCC values.
§ §