Intel PCH-LP, Programming Manual

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Flash Programming Tool
8.3.4 Block Erase Size (in Bytes - 256B, 4K, 64K)
This tells FPT how to properly configure PCH family parts to set the correct erase
granularity, or in other words how big of a block gets erased at a time. This value is
limited by the flash part and the PCH SPI controller: 256 B, 4 KB or 64 KB.
The SPI flash’s data sheet will tell what erase granularity is supported.
For Broadwell PCH-LP Platforms, the only granularity supported will be 4 KB.
This field is notated in hexadecimal notation. The choices for this field are: 0x100,
0x1000 (default), or 0x10000.
8.3.5 Block Erase Command
This field is the erase command opcode that FPT will use. After the Block Erase size is
chosen, use the corresponding opcode in this field. This is a one byte opcode in
hexadecimal notation.
For example: 0x20 if the opcode is 20h.
8.3.6 Write Granularity (1 or 64)
This field dictates how many bytes will be written for each write command.
Broadwell PCH-LP only supports 1 or 64 B writes. Flash devices that allow writes more
than a single byte at a time usually support up to 256 bytes at a time. Look to see how
many bytes the 02h opcode can support.
64 B has much better write performance, but if any issues are noted, set this field to 1
B write.
This field is in decimal notation. The choices for this field are: 1 or 64.
8.3.7 Enable Write Status /Unused
Legacy flash parts may only be able to use 50h opcode in order to unlock the status
register. Unlocking the status register is described in detail in section
412H
6.1 Unlocking SPI
Flash Device Protection for Broadwell PCH-LP Platform This bit should not be set for
most flash parts, only those that do not support 06h opcode for unlocking the status
register.
8.3.8 Chip Erase Command
This command is the one that is used to erase the entire flash part when FPT is used
with the /c option. This field is in hexadecimal notation.
Example: 0xC7
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