Intel PCH-LP, Programming Manual

Page: 48 / 90

48 523462
Intel Confidential
Configuring BIOS/GbE for SPI Flash Access
Table 6-4. VSCC1 - Vendor Specific Component Capabilities Register for SPI Component 1
(Sheet 1 of 2)
Bit Description
31
Component Property Parameter Table Valid (CPPTV) - RO:
This bit is set to a 1 if the Flash Controller detects a valid SFDP Component Property Parameter
Table in SPI Component 1
If CPPTV bit is ‘0’, software must configure the VSCC register appropriately. If CPPTV bit is ‘1’, the
corresponding parameter values discovered via SFDP will be used. In most cases, software is not
required to configure the VSCC register. However, if the SFDP table indicates an erase size other
than 4k byte, then the software is required to program the VSCC.EO register with the correct erase
opcode.
30:16 Reserved
15:8
Erase Opcode (EO)— RW:
This register is programmed with the Flash erase instruction opcode required by the vendor’s Flash
component.
This register is locked by the Vendor Component Lock (VCL) bit.
7:5
Quad Enable Requirements (QER)
000 = Part does not require a Quad Enable bit to be set, either because Quad is not supported or
because the manufacturer permanently enables Quad capability (e.g. Micron, Numonyx).
001 = Part requires bit 9 in status register 2 to be set to enable quad IO. Writing one byte to status
register clears all bits in register 2, therefore status register writes MUST be two bytes. If the
status register is unlocked and SFDP bits WSR or VSCC WSR is 1 then SPI controller cannot
use the quad output, quad IO features of this part because the hardware will automatically
write one byte of zeros to status register with every write/erase. (e.g. Winbond, AMIC,
Spansion).
010 = Part requires bit 6 of status register 1 to be set to enable quad IO. If the status register is
unlocked and SFDP WSR bit or VSCC WSR is 1 then flash controller cannot use the quad out-
put, quad IO features of this part because the hardware will automatically write one byte of
zeros to status register with every write/erase (e.g. Macronix).
011 = Part requires bit 7 of the configuration register to be set to enable Quad (e.g. Atmel).
100 = Part requires bit 9 in status register 2 to be set to enable quad IO. Writing one byte to the
status register does not clear the second byte (SST/Microchip, Winbond).
Note: This register is locked by the Vendor Component Lock (VCL) bit.
4
Write Enable on Write to Status (WEWS) — RW:
‘0’ = 50h will be the opcode used to unlock the status register if WSR (bit 3) is set to 1b.
‘1’ = 06h will be the opcode used to unlock the status register if WSR (bit 3) is set to 1b.
This register is locked by the Vendor Component Lock (VCL) bit.
Please refer to
Table 6-5
for a description of how these bits is used.