Intel PCH-LP, Programming Manual

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PCH SPI Flash Compatibility Requirement
3.1.2 Integrated LAN Firmware SPI Flash Requirements
A serial flash device that will be used for system BIOS and Integrated LAN or
Integrated LAN only must meet all the SPI Based BIOS Requirements plus:
Must support “Hardware Sequencing Requirements” .
4 KBytes erase capability must be supported.
3.1.2.1 SPI Flash Unlocking Requirements for Integrated LAN
BIOS must ensure there is no SPI flash based read/write/erase protection on the GbE
region. GbE firmware and drivers for the integrated LAN need to be able to read, write
and erase the GbE region at all times.
3.1.3 Intel
®
Management Engine Firmware (Intel
®
ME FW) SPI
Flash Requirements
Intel Management Firmware must meet the SPI flash based BIOS Requirements plus:
3.1.4 SFDP
3.1.5 JEDEC ID (Opcode 9Fh)
3.1.6 Multiple Page Write Usage Model
3.1.7 Hardware Sequencing Requirements
Flash part must be uniform 4 KB erasable block throughout the entire part.
Write protection scheme must meet guidelines as defined in
317H
SPI Flash Unlocking
Requirements for Intel Management Engine .
SPI Flash Unlocking Requirements for Intel Management Engine
Flash devices must be globally unlocked (read, write and erase access on the ME
region) from power on by writing 00h to the flash’s status register to disable write
protection.
If the status register must be unprotected, it must use the enable write status register
command 50h or write enable 06h.
Opcode 01h (write to status register) must then be used to write a single byte of 00h
into the status register. This must unlock the entire part. If the SPI flash’s status
register has non-volatile bits that must be written to, bits [5:2] of the flash’s status
register must be all 0h to indicate that the flash is unlocked.
If there is no need to execute a write enable on the status register, then opcodes 06h
and 50h must be ignored.
After global unlock, BIOS has the ability to lock down small sections of the flash as long
as they do not involve the ME or GbE region. See
318H
6.1 Unlocking SPI Flash Device
Protection for Broadwell PCH-LP Platform and
320H321H
6.2 Locking SPI Flash via Status Register
for more information about flash based write/erase protection.