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523462

Intel Confidential

APPENDIX A - Descriptor Configuration

APPENDIX A - Descriptor

Configuration

A.1

Flash Descriptor PCH Soft Strap Section

The following section describes functionality and how to set soft strapping for a target
platform. Improper setting of soft straps can lead to undesired operation and may lead to
returns/recalls.

Only default values that will be provided are for softstraps that are reserved.

Summary of Contents for PCH-LP

Page 1: ...Document Number Broadwell Platform Controller Hub Low Power PCH LP SPI Programming Guide June 2014 Revision 1 0 Intel Confidential...

Page 2: ...http www intel com design literature htm Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release Customers licensee...

Page 3: ...h 17 3 1 6 Multiple Page Write Usage Model 17 3 1 7 Hardware Sequencing Requirements 18 3 2 Broadwell PCH LP SPI AC Electrical Compatibility Guidelines 19 3 3 SPI Flash DC Electrical Compatibility Gui...

Page 4: ...ontrol 36 4 3 1 Intel Recommended Permissions for Region Access 37 4 3 2 Overriding Region Access 37 4 4 Intel ME Vendor Specific Component Capabilities Intel ME VSCC Table 38 4 4 1 How to Set a JEDEC...

Page 5: ...A Descriptor Configuration 73 A 1 Flash Descriptor PCH Soft Strap Section 73 A 2 PCHSTRP0 Strap 0 Record Flash Descriptor Records 74 A 3 PCHSTRP1 Strap 1 Record Flash Descriptor Records 76 A 4 PCHSTR...

Page 6: ...ove VSCC Table Entry 57 Tables 1 1 Terminology 10 1 2 Reference Documents 10 2 1 Region Size vs Erase Granularity of Flash Components 13 3 1 SPI Timings 20 MHz 19 3 2 SPI Timings 33 MHz 19 3 3 SPI Tim...

Page 7: ...n Number Description Date 523462 0 5 Initial release of document April 2013 0 7 Added section 4 1 2 3 for flash invalid instructions 4 7 August 2013 0 9 Updated section 6 4 table 6 1 and table 6 2 Sep...

Page 8: ...Intel Confidential 8...

Page 9: ...inition Chapter 6 Configuring BIOS GbE for SPI Flash Access Describes how to configure BIOS GbE for SPI flash access Chapter 7 Flash Image Tool This tool creates a descriptor and combines the GBE BIOS...

Page 10: ...op and PCHnM mobile LPC Low Pin Count Bus bus on where legacy devices such a FWH reside PCH LP Platform Controller Hub Low Power SPI Serial Peripheral Interface refers to serial flash memory in this d...

Page 11: ...sh Discoverable Parameter SFDP Broadwell PCH LP supports SPI with SFDP SFDP Serial Flash Discoverable Parameter is a JEDEC standard provides a consistent method of describing the functional and featur...

Page 12: ...t will determine the location of BIOS through the base address that is defined in the SPI flash descriptor See 113H287HChapter 4 Descriptor Overview and for more detailed information 2 6 Flash Regions...

Page 13: ...defaults to hardware sequencing Hardware sequencing has a predefined list of opcodes with only the erase opcode being programmable This mode is only available if the descriptor is present and valid In...

Page 14: ...14 523462 Intel Confidential PCH SPI Flash Architecture...

Page 15: ...ead in order to enable Fast Read in PCH 3 1 1 SPI based BIOS Requirements Erase size capability of 4 KBytes Serial flash device must ignore the upper address bits such that an address of FFFFFFh alias...

Page 16: ...guidelines as defined in 317H SPI Flash Unlocking Requirements for Intel Management Engine SPI Flash Unlocking Requirements for Intel Management Engine Flash devices must be globally unlocked read wr...

Page 17: ...is available on the JEDEC website www jedec org 3 1 6 Multiple Page Write Usage Model Intel platforms have firmware usage models require that the serial flash device support multiple writes to a page...

Page 18: ...software Read Data 03h Write Disable 04h Read Status 05h Outputs contents of SPI flash s status register Write Enable 06h Fast Read 0Bh Enable Write to Status Register 50h or 06h Enables a bit in the...

Page 19: ...ith respect to serial clock falling edge at the host 0 ns t186a Setup of SPI_CS 1 0 assertion with respect to serial clock rising edge at the host 30 ns t187a Hold of SPI_CS 1 0 assertion with respect...

Page 20: ...Clock Frequency 50 MHz Operation 46 99 53 40 MHz 1 t183c Tco of SPI_MOSI with respect to serial clock falling edge at the host 3 3 ns t184c Setup of SPI_MISO with respect to serial clock falling edge...

Page 21: ...race See Figure 3 3 for more detail Parameter Min Max Units Notes Supply Voltage Vcc 3 14 3 7 V Input High Voltage 0 5 VCC VCC 0 5 V Input Low Voltage 0 5 0 3 VCC V Output High Characteristics 0 9 VCC...

Page 22: ...22 523462 Intel Confidential PCH SPI Flash Compatibility Requirement...

Page 23: ...isters The maximum size of the Flash Descriptor is 4 KBytes It requires its own discrete erase block so it may need greater than 4 KBytes of flash space depending on the flash architecture that is on...

Page 24: ...Reserved region is for future chipset usage The Descriptor Upper Map determines the length and base address of the Intel ME VSCC Table The Intel ME VSCC Table holds the JEDEC ID and the ME VSCC infor...

Page 25: ...ponent requires a separate chip select 00 1 Component 01 2 Components All other settings Reserved 7 0 Flash Component Base Address FCBA This identifies address bits 11 4 for the Component portion of t...

Page 26: ...and bits 3 0 are 0 Set this field to 20h This will define FCPUSBA as 200h Bits Description 31 Reserved 30 Dual Output Fast Read Support 0 Dual Output Fast Read is not supported 1 Dual Output Fast Rea...

Page 27: ...ing to 50 MHz ensure flash meets timing requirements defined in Table 3 3 20 Fast Read Support 0 Fast Read is not Supported 1 Fast Read is supported If the Fast Read Support bit is a 1 and a device is...

Page 28: ...he PCH 0000 512 KB 0001 1 MB 0010 2 MB 0011 4 MB 0100 8 MB 0101 16 MB 0110 32 MB 0111 64 MB 1000 1111 Reserved Note This field is defaulted to 0101b 16MB_ after reset Bits Description Bits Description...

Page 29: ...IOS Register Flash Descriptor Records Memory Address FRBA 004h Size 32 bits Bits Description 31 Reserved 30 16 Region Limit This specifies bits 26 12 of the ending address for this Region Notes 1 Set...

Page 30: ...ts 26 12 for the Region Base Bits Description 31 Reserved 30 16 Region Limit This specifies bits 26 12 of the ending address for this Region Notes 1 The maximum Region Limit is 128KB above the region...

Page 31: ...e Function 0 0 0 Bits Description 31 24 Master Region Write Access Each bit 31 24 corresponds to Regions 7 0 If the bit is set this master can erase and write that particular region through register a...

Page 32: ...4 4 Intel ME Vendor Specific Component Capabilities Intel ME VSCC Table for information on how to program individual entries 4 1 7 1 JID0 JEDEC ID 0 Register Flash Descriptor Records Memory Address VT...

Page 33: ...cturer permanently enables Quad capability e g Micron Numonyx 001 Part requires bit 9 in status register 2 to be set to enable quad IO Writing one byte to status register clears all bits in register 2...

Page 34: ...Flash Component This is the third byte returned by the Read JEDEC ID command opcode 9Fh 15 8 SPI Component Device ID 0 This field identifies the first byte of the Device ID of the SPI Flash Component...

Page 35: ...e manufacturer permanently enables Quad capability e g Micron Numonyx 001 Part requires bit 9 in status register 2 to be set to enable quad IO Writing one byte to status register clears all bits in re...

Page 36: ...ly three masters that have the ability to access other regions CPU BIOS Intel ME Firmware and GbE software driver running on CPU Notes 1 Descriptor and PDR regions are not masters so they will not hav...

Page 37: ...riptor override strap This strap should only be visible and available in manufacturing or during product development After this strap has been set you can use a host based flash programming tool like...

Page 38: ...tor Records thru 4 1 7 4 VSCCn Vendor Specific Component Capabilities n Flash Descriptor Records 4 4 2 How to Set a VSCC Entry in Intel ME VSCC Table for Broadwell PCH LP Platforms VSCC0 needs to be p...

Page 39: ...ad capability e g Micron Numonyx 001 Part requires bit 9 in status register 2 to be set to enable quad IO Writing one byte to status register clears all bits in register 2 therefore status register wr...

Page 40: ...egister Opcodes sequence sent to SPI flash will bit 06h WSR or WEWS should be not be set on devices that use non volatile memory for their status register Setting this bit will cause operations to be...

Page 41: ...ycle The discoverable parameter read opcode behaves like a fast read command The opcode is 5Ah and the address cycle is 24 bit long After the opcode 5Ah is clocked in there are 24 bit of address clock...

Page 42: ...eter values indicate that they are supported These capabilities are not supported as default Quad I O Read Quad Output Read Dual I O read Block Sector Erase size Note If SFDP is valid and advertises 4...

Page 43: ...ime than a write to volatile memory During this write the flash part will ignore all commands but a read to the status register opcode 05h The output of the read status register command will tell the...

Page 44: ...egister to lock down the factory default portion of Intel ME Ignition FW region The runtime portion should be left unprotected as to allow BIOS to update it It is strongly recommended that if Flash De...

Page 45: ...s are located in the BIOS GbE VSCC0 registers VCL applies the lock to both VSCC0 and VSCC1 even if VSCC1 is not used Without the VCL bits set it is possible to make Host GbE VSCC register s changes in...

Page 46: ...e instruction opcode required by the vendor s Flash component Software must program this register if the SFDP table for this component does not show 4 kByte erase capability This register is locked by...

Page 47: ...WG RW 0 1 Byte 1 64 Byte This register is locked by the Vendor Component Lock VCL bit Notes 1 If more than one Flash component exists this field must be set to the lowest common write granularity of t...

Page 48: ...to enable quad IO Writing one byte to status register clears all bits in register 2 therefore status register writes MUST be two bytes If the status register is unlocked and SFDP bits WSR or VSCC WSR...

Page 49: ...by the Vendor Component Lock VCL bit If more than one Flash component exists this field must be set to the lowest common write granularity of the different Flash components If using 64 B write BIOS mu...

Page 50: ...bit high requires that BIOS ensure that no multiple byte write operation does not cross a 256 Byte page boundary as it will have unintended results This is a feature of page programming capable flash...

Page 51: ...us chipset parameters to match the target hardware Different configurations can be saved to a file so image layouts do not need to be recreated each time The user does not need to interact with the GU...

Page 52: ...assigned a fixed amount of space If no fixed space is assigned then the region occupies only as much space as it requires 2 If after allocation for all regions there is still space left in flash then...

Page 53: ...k Ok to update the parameter Some SPI flash devices support both standard and fast read opcodes Fast reads are able to operate at faster frequencies than the regular reads For PCH to support these fas...

Page 54: ...ponent size from the drop down list Click OK to update the parameters Note The size of the second flash component will only be editable if the number of flash components is set to 2 The Upper and Lowe...

Page 55: ...e parameters for GbE LAN master access recommended for production phase It will lock down descriptor region with a necessary level of security for Intel ME enabled systems There are recommended settin...

Page 56: ...l ME VSCC Table This information provided is dependent on the flash device used on the system for more information Please contact your flash vendor for information on the specific SPI flash device 7 4...

Page 57: ...See 34 4 Intel ME Vendor Specific Component Capabilities Intel ME VSCC Table for more detailed information on how to set the VSCC register value 7 4 2 Removing an Existing Table Entry To remove an ex...

Page 58: ...58 523462 Intel Confidential Flash Image Tool...

Page 59: ...e Sequencing Opcode Recommendations and 6 3 SPI Protected Range Register Recommendations for more details 8 2 Fparts txt File This text file contains a list of all flash devices that this tool support...

Page 60: ...amming tool identifies a flash part FPT cycles through three opcodes in order to find a matching entry JEDEC ID 9Fh Read ID 90h or ABh JEDEC ID is a three byte sequence which the industry standard opc...

Page 61: ...6 Write Granularity 1 or 64 This field dictates how many bytes will be written for each write command Broadwell PCH LP only supports 1 or 64 B writes Flash devices that allow writes more than a single...

Page 62: ...62 523462 Intel Confidential Flash Programming Tool...

Page 63: ...ough to accommodate the intended image 1 MByte BIOS image 1MB bin 2 MByte SPI flash on platform 9 1 1 Example of SPI flash programming In system programming If BIOS image size is an even factor of the...

Page 64: ...64 523462 Intel Confidential SPI Flash Programming Procedures...

Page 65: ...I ME region unlock There is a HECI command that allows Intel ME FW to boot up in a temporarily disabled state and allows for a host program to overwrite the ME region Note Removing the DIMM from chann...

Page 66: ...66 523462 Intel Confidential Intel ME Disable for Debug Flash Burning Purposes...

Page 67: ...programming SPI flash where the system is not powered will not result in any interference from Intel ME FW The following methods are for Intel ME FW Program via In Circuit Test System is not fully po...

Page 68: ...68 523462 Intel Confidential Recommendations for SPI Flash Programming in Manufacturing Environments...

Page 69: ...are intended to be used by the platform must have an entry in Intel ME VSCC table This allows the ability for the OEM ODM to add Intel ME support to any flash parts that meet the requirements defined...

Page 70: ...see 4511 Recommendations for SPI Flash Programming in Manufacturing Environments for more information There are also other system activities beside the Intel ME that can change the data on the flash...

Page 71: ...may have to reflash the descriptor to get the proper access Q What does following FPT error message mean Error Flash program registers are locked HSFSTS 15 FLOCKDN A The Flash Configuration Lock Down...

Page 72: ...SPI1234 ID 0x123456 Size 4096KB 32768Kb Device ID 0xFFFF not supported Error 405 There is no supported SPI flash device installed This error will result when the descriptor has two flash parts defined...

Page 73: ...sh Descriptor PCH Soft Strap Section The following section describes functionality and how to set soft strapping for a target platform Improper setting of soft straps can lead to undesired operation a...

Page 74: ...access to Serial Flash 0 DMI RequesterID Checks are enabled 1 DMI RequesterID Checks are disabled No Requester ID checking is done on accesses from DMI This bit is only applicable for platforms that...

Page 75: ...processor Note This setting is not the same for all designs is dependent on the board design The setting of this field must be determined by the BIOS developer and the platform hardware designer 8 SM...

Page 76: ...d is enabled Default This soft strap only has effect if Dual Output read is discovered as supported via the SFDP If parameter table is not detected via SFDP this bit has no effect and Dual Output Read...

Page 77: ...CTP Address is disabled 1 Intel ME SMBus MCTP Address is enabled Note This field is only used for testing purposes on Intel ME FW This field should only be set to 1 for testing purposes on platforms t...

Page 78: ...e This field must be programmed to 64h This is the Intel PHY s SMBus address This field must be programmed to 64h GbE PHY SMBus Address and GbE MAC address have to be programmed to 64h and 70h in orde...

Page 79: ...ired LAN solution then this field must be set to 0 7 2 Reserved set to 0 1 0 Intel PHY Connectivity PHYCON 1 0 This field determines if Intel wired PHY is connected to SMLink0 00 No Intel wired PHY co...

Page 80: ...scription Usage 31 0 Reserved set to 0 Bits Description Usage 31 0 Intel ME SMBus Subsystem Vendor and Device ID MESMA2UDID MESMAUDID 15 0 Subsystem Vendor ID MESMAUDID 31 16 Subsystem Device ID The v...

Page 81: ...rt 1 Mode USB3P3_PCIEP1_MODE 00 PCIe Lane 1 is statically assigned to PCI Express or GbE 01 PCIe Lane 1 is statically assigned to USB3 Port 3 10 Reserved 11 Reserved This soft strap sets the default v...

Page 82: ...lane reversal 4 PCIe Lane Reversal 1 PCIELR1 This bit lane reversal behavior for PCIe Port 1 if configured as a x4 PCIe port 0 PCIe Lanes 0 3 are not reversed 1 PCIe Lanes 0 3 are reversed when Port 1...

Page 83: ...able 15 9 ME Debug SMBus Emergency Mode Address MDSMBE_ADD SMBUS address used for ME Debug status writes If this field is 00h the default address 38h is used Note Please set this field 00h by default...

Page 84: ...thermal reporting then this field must be set to 0 Note This setting is not the same for all designs is dependent on the board design The setting of this field must be determined by the BIOS developer...

Page 85: ...1 Pins assigned to Native mode SML1Data SML1Clk This setting determines if the GPIO74 and GPIO75 pins are assigned to Native mode or assigned to GPIO 29 27 Chipset configuration set to 011b 26 23 Chi...

Page 86: ...trap is set to 11 then GPIO34 native mode is SATA0_PCIE6L3 else the native mode is SATA0GP 7 6 SATA Port 1 PCIe Port 6 Lane 2 Mode SATAP1_PCIEP6L2_MODE 00 Statically assigned to SATA Port 1 01 Statica...

Page 87: ...O3 Select SLP_WLAN _GP29MGPIO3_SEL 0 SLP_WLAN 1 GPIO29 MGPIO3 14 SMLink1 Thermal Reporting Select SMLINK1_THERM_SEL 0 Reserved 1 PCH temperature 1 byte of data will be available for polling out on SML...

Page 88: ...BA 044h Size 32 bits Default Flash Address 144h Recommended Value A 20 PCHSTRP18 Strap 18 Record Flash Descriptor Records Flash Address FPSBA 048h Size 32 bits Default Flash Address 148h Recommended V...

Page 89: ...HY Power Control 0 Set as SATA MPHY Power Control SATAPC Default 1 Enable SATA Port 1 PCIe Port 6 Lane 2 Mode SATAP1_PCIEP6L2_MODE This strap configures the default state of GPIO35 SATAP1_PCIE6L2B_MOD...

Page 90: ...ial APPENDIX A Descriptor Configuration A 23 CPUSTRP0 Strap 0 Record Flash Descriptor Records Flash Address FCPUSBA 000h Size 32 bits Default Flash Address 200h Recommended Value Bits Description Usag...

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