Intel PCH-LP, Programming Manual

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Configuring BIOS/GbE for SPI Flash Access
6 Configuring BIOS/GbE for SPI
Flash Access
6.1 Unlocking SPI Flash Device Protection for
Broadwell PCH-LP Platform
BIOS must account for any built in protection from the flash device itself. BIOS must
ensure that any flash based protection will only apply to BIOS region only. It should not
affect the ME or GbE regions.
All the SPI flash devices that meet the SPI flash requirements in the Broadwell PCH-LP
Family External Design Specification (EDS) will be unlocked by writing a 00h to the SPI
flash’s status register. This command must be done via an atomic software sequencing
to account for differences in flash architecture. Atomic cycles are uninterrupted in that
it does not allow other commands to execute until a read status command returns a
‘not busy’ result from the flash.
Some flash vendors implement their status registers in NVM flash (non-volatile
memory). This takes much more time than a write to volatile memory. During this
write, the flash part will ignore all commands but a read to the status register (opcode
05h). The output of the read status register command will tell the PCH when the
transaction is done.
Recommended flash unlocking sequence:
• Write enable (06h) command will have to be in the prefix opcode configuration
register.
• The “write to status register” opcode (01h) will need to be an opcode menu
configuration option.
• Opcode type for write to status register will be ‘01’: a write cycle type with no
address needed.
• The FDATA0 register should to be programmed to 0000 0000h.
• Data Byte Count (DBC) in Software Sequencing Flash Control register should be
000000b. Errors may occur if any non zero value is here.
• Set the Cycle Opcode Pointer (COP) to the “write to status register” opcode.
• Set to Sequence Prefix Opcode Pointer (SPOP) to Write Enable.
• Set the Data Cycle (DS) to 1.
• Set the Atomic Cycle Sequence (ACS) bit to 1.
• To execute sequence, set the SPI Cycle Go bit to 1.
Please see the Serial Peripheral Interface Memory Mapped Configuration
Registers in the Broadwell PCH-LP Family External Design Specification (EDS) for
more detailed information.