Intel PCH-LP, Programming Manual

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Configuring BIOS/GbE for SPI Flash Access
size of SPI component 0 (C0DEN). When FLA <= C0DEN then VSCC0 will be used;
whereas FLA > C0DEN then VSCC1 will be used If one SPI flash component used in the
system, VSCC0 needs to be set.
Refer to VSCC— Lower Vendor Specific Component Capabilities Register and in
the Broadwell PCH-LP Family External Design Specification (EDS).
See text below the tables for explanation on how to determine VSCC register values.
Table 6-3. VSCC0 - Vendor-Specific Component Capabilities Register for SPI Component
0 (Sheet 1 of 2)
Bit Description
31
Component Property Parameter Table Valid (CPPTV) - RO:
This bit is set to a 1 if the Flash Controller detects a valid SFDP Component Property Parameter
Table in SPI Component 0
If CPPTV bit is ‘0’, software must configure the VSCC register appropriately. If CPPTV bit is ‘1’, the
corresponding parameter values discovered via SFDP will be used. In most cases, software is not
required to configure the VSCC register. However, if the SFDP table indicates an erase size other
than 4k byte, then the software is required to program the VSCC.EO register with the correct erase
opcode.
30:24 Reserved
23
Vendor Component Lock (VCL): — RW/L:
'0': The lock bit is not set
'1': The Vendor Component Lock bit is set.
This register locks itself when set.
This bit applies to both VSCC0 and VSCC1
All bits locked by (VCL) will remained locked until a global reset.
22:16 Reserved
15:8
Erase Opcode (EO)— RW:
This register is programmed with the Flash erase instruction opcode required by the vendor’s Flash
component. Software must program this register if the SFDP table for this component does not
show 4 kByte erase capability
This register is locked by the Vendor Component Lock (VCL) bit.
Note: If CPPTV is 1 and the SPDP0 table shows 4k erase capability, the SFDP0 erase code is used
instead of this register
7:5
Quad Enable Requirements (QER)
000 = Part does not require a Quad Enable bit to be set, either because Quad is not supported or
because the manufacturer permanently enables Quad capability (e.g. Micron, Numonyx).
001 = Part requires bit 9 in status register 2 to be set to enable quad IO. Writing one byte to status
register clears all bits in register 2, therefore status register writes MUST be two bytes. If the
status register is unlocked and SFDP bits WSR or VSCC WSR is 1 then SPI controller cannot
use the quad output, quad IO features of this part because the hardware will automatically
write one byte of zeros to status register with every write/erase. (e.g. Winbond, AMIC,
Spansion).
010 = Part requires bit 6 of status register 1 to be set to enable quad IO. If the status register is
unlocked and SFDP WSR bit or VSCC WSR is 1 then flash controller cannot use the quad out-
put, quad IO features of this part because the hardware will automatically write one byte of
zeros to status register with every write/erase (e.g. Macronix).
011 = Part requires bit 7 of the configuration register to be set to enable Quad (e.g. Atmel).
100 = Part requires bit 9 in status register 2 to be set to enable quad IO. Writing one byte to the
status register does not clear the second byte (SST/Microchip, Winbond).
Note: This register is locked by the Vendor Component Lock (VCL) bit.