GigaDevice Semiconductor GD32VF103 User Manual Download Page 307

Page: 307 / 536

GD32VF103 User Manual

307

011: Toggle on match. O0CPRE toggles when the counter matches the output

compare register TIMERx_CH0CV.

100: Force low. O0CPRE is forced low level.

101: Force high. O0CPRE is forced high level.

110: PWM mode0. When counting up, O0CPRE is active as long as the counter is

smaller than TIMERx_CH0CV else inactive. When counting down, O0CPRE is

inactive as long as the counter is larger than TIMERx_CH0CV else active.

111: PWM mode1. When counting up, O0CPRE is inactive as long as the counter

is smaller than TIMERx_CH0CV else active. When counting down, O0CPRE is

active as long as the counter is larger than TIMERx_CH0CV else inactive.

When configured in PWM mode, the O0CPRE level changes only when the output

compare mode switches from “Timing mode” mode to “PWM” mode or when the

result of the comparison changes.

This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is

11 and CH0MS bit-filed is 00(COMPARE MODE).

CH0COMSEN

Channel 0 compare output shadow enable

When this bit is set, the shadow register of TIMERx_CH0CV register, which updates

at each update event, will be enabled.

0: Channel 0 output compare shadow disable

1: Channel 0 output compare shadow enable

The PWM mode can be used without validating the shadow register only in single

pulse mode (SPM bit in TIMERx_CTL0 register is set).

This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is

11 and CH0MS bit-filed is 00.

CH0COMFEN

Channel 0 output compare fast enable

When this bit is set, the effect of an event on the trigger in input on the

capture/compare output will be accelerated if the channel is configured in PWM0 or

PWM1 mode. The output channel will treat an active edge on the trigger input as a

compare match, and CH0_O is set to the compare level independently from the

result of the comparison.

0: Channel 0 output quickly compare disable. The minimum delay from an edge on

the trigger input to activate CH0_O

output is 5 clock cycles.

1: Channel 0 output quickly compare enable. The minimum delay from an edge on

the trigger input to activate CH0_O

output is 3 clock cycles.

1:0

CH0MS[1:0]

Channel 0 I/O mode selection

This bit-field specifies the work mode of the channel and the input signal selection.

This bit-field is writable only when the channel is not active. (CH0EN bit in

TIMERx_CHCTL2 register is reset).).

00: Channel 0 is configured as output

01: Channel 0 is configured as input, IS0 is connected to CI0FE0

10: Channel 0 is configured as input, IS0 is connected to CI1FE0

11: Channel 0 is configured as input, IS0 is connected to ITS. This mode is working

Summary of Contents for GD32VF103

Page 1: ...GD32VF103 User Manual 1 GigaDevice Semiconductor Inc GD32VF103 RISC V 32 bit MCU User Manual Revision 1 0 Jun 2019 ...

Page 2: ...view 32 2 2 Characteristics 32 2 3 Function overview 32 2 3 1 Flash memory architecture 32 2 3 2 Read operations 33 2 3 3 Unlock the FMC_CTL registers 33 2 3 4 Page erase 33 2 3 5 Mass erase 34 2 3 6 Main flash programming 35 2 3 7 Option bytes Erase 37 2 3 8 Option bytes modify 38 2 3 9 Option bytes description 38 2 3 10 Page erase program protection 39 2 3 11 Security protection 40 2 4 Register ...

Page 3: ...racteristics 57 4 3 Function overview 57 4 3 1 RTC clock calibration 57 4 3 2 Tamper detection 58 4 4 Register definition 59 4 4 1 Backup data register x BKP_DATAx x 0 41 59 4 4 2 RTC signal output control register BKP_OCTL 59 4 4 3 Tamper pin control register BKP_TPCTL 60 4 4 4 Tamper control and status register BKP_TPCS 60 5 Reset and clock unit RCU 62 5 1 Reset control unit RCTL 62 5 1 1 Overvi...

Page 4: ...nterrupt enable register EXTI_INTEN 99 6 6 2 Event enable register EXTI_EVEN 99 6 6 3 Rising edge trigger enable register EXTI_RTEN 100 6 6 4 Falling edge trigger enable register EXTI_FTEN 100 6 6 5 Software interrupt event register EXTI_SWIEV 101 6 6 6 Pending register EXTI_PD 101 7 General purpose and alternate function I Os GPIO and AFIO 102 7 1 Overview 102 7 2 Characteristics 102 7 3 Function...

Page 5: ...E 118 7 5 8 Event control register AFIO_EC 119 7 5 9 AFIO port configuration register 0 AFIO_PCF0 120 7 5 10 EXTI sources selection register 0 AFIO_EXTISS0 123 7 5 11 EXTI sources selection register 1 AFIO_EXTISS1 124 7 5 12 EXTI sources selection register 2 AFIO_EXTISS2 125 7 5 13 EXTI sources selection register 3 AFIO_EXTISS3 126 7 5 14 AFIO port configuration register 1 AFIO_PCF1 127 8 CRC calc...

Page 6: ...aisy chained structure 148 10 2 3 Debug reset 149 10 3 Debug hold function overview 149 10 3 1 Debug support for power saving mode 149 10 3 2 Debug support for TIMER I2C WWDGT FWDGT and CAN 149 10 4 Register definition 150 10 4 1 ID code register DBG_ID 150 10 4 2 Control register DBG_CTL 150 11 Analog to digital converter ADC 153 11 1 Introduction 153 11 2 Main features 153 11 3 Pins and internal...

Page 7: ...DC_SAMPT0 179 11 8 5 Sample time register 1 ADC_SAMPT1 180 11 8 6 Inserted channel data offset register x ADC_IOFFx x 0 3 181 11 8 7 Watchdog high threshold register ADC_WDHT 181 11 8 8 Watchdog low threshold register ADC_WDLT 182 11 8 9 Regular sequence register 0 ADC_RSQ0 182 11 8 10 Regular sequence register 1 ADC_RSQ1 183 11 8 11 Regular sequence register 2 ADC_RSQ2 183 11 8 12 Inserted sequen...

Page 8: ...199 12 4 11 DAC concurrent mode 8 bit right aligned data holding register DACC_R8DH 200 12 4 12 DAC0 data output register DAC0_DO 200 12 4 13 DAC1 data output register DAC1_DO 201 13 Watchdog timer WDGT 202 13 1 Free watchdog timer FWDGT 202 13 1 1 Overview 202 13 1 2 Characteristics 202 13 1 3 Function overview 202 13 1 4 Register definition 205 13 2 Window watchdog timer WWDGT 208 13 2 1 Overvie...

Page 9: ...rview 280 15 2 5 TIMERx registers x 1 2 3 4 297 15 3 Basic timer TIMERx x 5 6 318 15 3 1 Overview 318 15 3 2 Characteristics 318 15 3 3 Block diagram 318 15 3 4 Function overview 318 15 3 5 TIMERx registers x 5 6 323 16 Universal synchronous asynchronous receiver transmitter USART 328 16 1 Overview 328 16 2 Characteristics 328 16 3 Function overview 329 16 3 1 USART frame format 330 16 3 2 Baud ra...

Page 10: ...ication flow 357 17 3 7 Programming model 358 17 3 8 SCL line stretching 367 17 3 9 Use DMA for data transfer 368 17 3 10 Packet error checking 368 17 3 11 SMBus support 368 17 3 12 Status errors and interrupts 370 17 4 Register definition 371 17 4 1 Control register 0 I2C_CTL0 371 17 4 2 Control register 1 I2C_CTL1 373 17 4 3 Slave address register 0 I2C_SADDR0 374 17 4 4 Slave address register 1...

Page 11: ... 18 10 I2S interrupts 404 18 10 1 Status flags 404 18 10 2 Error flags 404 18 11 Register definition 406 18 11 1 Control register 0 SPI_CTL0 406 18 11 2 Control register 1 SPI_CTL1 408 18 11 3 Status register SPI_STAT 409 18 11 4 Data register SPI_DATA 410 18 11 5 CRC polynomial register SPI_CRCPOLY 411 18 11 6 RX CRC register SPI_RCRC 411 18 11 7 TX CRC register SPI_TCRC 412 18 11 8 I2S control r...

Page 12: ...R 450 20 4 8 Bit timing register CAN_BT 451 20 4 9 Transmit mailbox identifier register CAN_TMIx x 0 2 452 20 4 10 Transmit mailbox property register CAN_TMPx x 0 2 453 20 4 11 Transmit mailbox data0 register CAN_TMDATA0x x 0 2 453 20 4 12 Transmit mailbox data1 register CAN_TMDATA1x x 0 2 454 20 4 13 Receive FIFO mailbox identifier register CAN_RFIFOMIx x 0 1 454 20 4 14 Receive FIFO mailbox prop...

Page 13: ... 3 USB device function 466 21 5 4 OTG function overview 467 21 5 5 Data FIFO 468 21 5 6 Operation guide 471 21 6 Interrupts 475 21 7 Register definition 477 21 7 1 Global control and status registers 477 21 7 2 Host control and status registers 498 21 7 3 Device control and status registers 510 21 7 4 Power and clock control register USBFS_PWRCLKCTL 534 22 Revision history 535 ...

Page 14: ...echanism 136 Figure 9 3 DMA interrupt logic 138 Figure 9 4 DMA0 request mapping 139 Figure 9 5 DMA1 request mapping 140 Figure 11 1 ADC module block diagram 154 Figure 11 2 Single conversion mode 156 Figure 11 3 Continuous conversion mode 157 Figure 11 4 Scan conversion mode continuous disable 158 Figure 11 5 Scan conversion mode continuous enable 159 Figure 11 6 Discontinuous conversion mode 160 ...

Page 15: ...Figure 15 8 Timing chart of center aligned counting mode 231 Figure 15 9 Repetition counter timing chart of center aligned counting mode 232 Figure 15 10 Repetition counter timing chart of up counting mode 232 Figure 15 11 Repetition counter timing chart of down counting mode 233 Figure 15 12 Input capture logic 234 Figure 15 13 Output compare logic with complementary output x 0 1 2 235 Figure 15 ...

Page 16: ...x_CHxCV 0x04 TIMERx_CAR 0x60 296 Figure 15 52 Basic timer block diagram 318 Figure 15 53 Normal mode internal clock divided by 1 319 Figure 15 54 Counter timing diagram with prescaler division change from 1 to 2 320 Figure 15 55 Timing chart of up counting mode PSC 0 1 321 Figure 15 56 Timing chart of up counting mode change TIMERx_CAR ongoing 322 Figure 16 1 USART module block diagram 330 Figure ...

Page 17: ...3 I2S Phillips standard timing diagram DTLEN 00 CHLEN 0 CKPL 1 392 Figure 18 14 I2S Phillips standard timing diagram DTLEN 10 CHLEN 1 CKPL 0 393 Figure 18 15 I2S Phillips standard timing diagram DTLEN 10 CHLEN 1 CKPL 1 393 Figure 18 16 I2S Phillips standard timing diagram DTLEN 01 CHLEN 1 CKPL 0 393 Figure 18 17 I2S Phillips standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 393 Figure 18 18 I2S Phil...

Page 18: ...43 PCM standard long frame synchronization mode timing diagram DTLEN 10 CHLEN 1 CKPL 1 399 Figure 18 44 PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 0 399 Figure 18 45 PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 1 399 Figure 18 46 PCM standard long frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 0 399 Figure...

Page 19: ...Figure 21 1 USBFS block diagram 462 Figure 21 2 Connection with host or device mode 463 Figure 21 3 Connection with OTG mode 464 Figure 21 4 State transition diagram of host port 464 Figure 21 5 HOST mode FIFO space in SRAM 469 Figure 21 6 Host mode FIFO access register map 469 Figure 21 7 Device mode FIFO space in SRAM 470 Figure 21 8 Device mode FIFO access register map 471 ...

Page 20: ...ART0 alternate function remapping 110 Table 7 10 USART1 alternate function remapping 110 Table 7 11 USART2 alternate function remapping 110 Table 7 12 I2C0 alternate function remapping 110 Table 7 13 SPI0 alternate function remapping 111 Table 7 14 SPI2 I2S2 alternate function remapping 111 Table 7 15 CAN0 alternate function remapping 111 Table 7 16 CAN1 alternate function remapping 111 Table 7 17...

Page 21: ...nductors 355 Table17 2 Event status flags 370 Table17 3 I2C error flags 370 Table 18 1 SPI signal description 381 Table 18 2 SPI operating modes 383 Table 18 3 SPI interrupt requests 390 Table 18 4 I2S bitrate calculation formulas 400 Table 18 5 Audio sampling frequency calculation formulas 400 Table 18 6 Direction of I2S interface signals for each operation mode 401 Table 18 7 I2S interrupt 405 T...

Page 22: ...ttle endian RV32IMAC 32GPRs Configurable 2 stage pipeline optimized for low gate count and high frequency Machine M and User U Privilege levels support Single cycle hardware multiplier and Multi cycles hardware divider support Misaligned load store hardware support Atomic instructions hardware support Non maskable interrupt NMI support Dynamic Branch Prediction and instruction pre fetch buffers to...

Page 23: ...F DBUS is the data bus of the RISC V core which is used for loading storing data and also for debugging access of the Code region Similarly SBUS is the system bus of the RISC V core which is used for fetching instruction vector loading storing data and debugging access of the system regions The System regions include the internal SRAM region and the Peripheral region DMA0 and DMA1 are the buses of...

Page 24: ...DO 1 2V IRC 8MHz HXTAL 3 25MHz LVD Powered By VDDA Master I2C0 I2C1 FWDGT RTC DAC TIMER4 6 GPIOC GPIOD GPIOE TIMER0 USART3 5 CAN1 ADC0 1 AHB Peripherals FMC USB FS CRC RCU GP DMA0 Slave EXMC 12 bit SAR ADC Powered By VDDA RISC_V CPU Fmax 108MHz JTAG System DCode ICode AHB Matrix APB2 Fmax 108MHz APB1 Fmax 54MHZ Master GP DMA1 1 3 Memory map The RISC V processor is structured using a Harvard archit...

Page 25: ...address decoding for each peripheral Table 1 2 Memory map of GD32VF103 devices Pre defined Regions Bus Address Peripherals External device AHB 0xA000 0000 0xA000 0FFF EXMC SWREG External RAM 0x9000 0000 0x9FFF FFFF Reserved 0x7000 0000 0x8FFF FFFF Reserved 0x6000 0000 0x6FFF FFFF EXMC NOR PSRAM SRA M Peripheral AHB 0x5000 0000 0x5003 FFFF USBFS 0x4008 0000 0x4FFF FFFF Reserved 0x4004 0000 0x4007 F...

Page 26: ...01 5BFF Reserved 0x4001 5400 0x4001 57FF Reserved 0x4001 5000 0x4001 53FF Reserved 0x4001 4C00 0x4001 4FFF Reserved 0x4001 4800 0x4001 4BFF Reserved 0x4001 4400 0x4001 47FF Reserved 0x4001 4000 0x4001 43FF Reserved 0x4001 3C00 0x4001 3FFF Reserved 0x4001 3800 0x4001 3BFF USART0 0x4001 3400 0x4001 37FF Reserved 0x4001 3000 0x4001 33FF SPI0 0x4001 2C00 0x4001 2FFF TIMER0 0x4001 2800 0x4001 2BFF ADC1...

Page 27: ...00 53FF UART4 0x4000 4C00 0x4000 4FFF UART3 0x4000 4800 0x4000 4BFF USART2 0x4000 4400 0x4000 47FF USART1 0x4000 4000 0x4000 43FF Reserved 0x4000 3C00 0x4000 3FFF SPI2 I2S2 0x4000 3800 0x4000 3BFF SPI1 I2S1 0x4000 3400 0x4000 37FF Reserved 0x4000 3000 0x4000 33FF FWDGT 0x4000 2C00 0x4000 2FFF WWDGT 0x4000 2800 0x4000 2BFF RTC 0x4000 2400 0x4000 27FF Reserved 0x4000 2000 0x4000 23FF Reserved 0x4000...

Page 28: ... FFFF Reserved 0x083C 0000 0x0FFF FFFF Reserved 0x0802 0000 0x083B FFFF Reserved 0x0800 0000 0x0801 FFFF Main Flash 0x0030 0000 0x07FF FFFF Reserved 0x0010 0000 0x002F FFFF Aliased to Main Flash or Boot loader 0x0002 0000 0x000F FFFF 0x0000 0000 0x0001 FFFF 1 3 1 On chip SRAM memory The GD32VF103 series of devices contain up to 32 KB of on chip SRAM which address starts at 0x2000 0000 It supports ...

Page 29: ...oot0 Main Flash Memory x 0 Boot loader 0 1 On chip SRAM 1 1 Note When the boot source is hoped to be set as Main Flash Memory the Boot0 pin has to be connected with GND definitely and can not be floating The embedded boot loader is located in the System memory which is used to reprogram the Flash memory In GD32VF103 devices the boot loader can be activated through the USART0 PA9 and PA10 USART1 PD...

Page 30: ...evice in Kbytes Example 0x0008 indicates 8 Kbytes 15 0 FLASH_DENSITY 15 0 Flash memory density The value indicates the Flash memory density of the device in Kbytes Example 0x0020 indicates 32 Kbytes 1 5 2 Unique device ID 96 bits Base address 0x1FFF F7E8 The value is factory programmed and can never be altered by user 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNIQUE_ID 31 16 r 15 14 13 12 11...

Page 31: ... 32 r Bits Fields Descriptions 31 0 UNIQUE_ID 63 32 Unique device ID Base address 0x1FFF F7F0 The value is factory programmed and can never be altered by user 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNIQUE_ID 95 80 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNIQUE_ID 79 64 r Bits Fields Descriptions 31 0 UNIQUE_ID 95 64 Unique device ID ...

Page 32: ... system reset Flash security protection to prevent illegal code data access Page erase program protection to prevent unexpected operation 2 3 Function overview 2 3 1 Flash memory architecture The flash memory consists of up to 128 KB main flash organized into 128 pages with 1 KB capacity per page and a 18 KB Information Block for the Boot Loader The main flash memory contains a total of up to 128 ...

Page 33: ...C_OBKEY register And then the hardware sets the OBWEN bit in FMC_CTL register to 1 The software can reset OBWEN bit to 0 to protect the OBPG bit and OBER bit in FMC_CTL register again 2 3 4 Page erase The FMC provides a page erase function which is used to initialize the contents of a main flash memory page to a high state Each page can be erased independently without affecting the contents of oth...

Page 34: ...ess of page erase operation Set the PER bit Write FMC_ADDR Is the LK bit is 0 Send the command to FMC by setting START bit Start Yes No Unlock the FMC_CTL Is the BUSY bit is 0 Yes No Is the BUSY bit is 0 Yes No Finish 2 3 5 Mass erase The FMC provides a complete erase function which is used to initialize the main flash block contents This erase can affect by setting MER bit to 1 in the FMC_CTL reg...

Page 35: ...ase operation can be implemented using a program that runs in SRAM or by using the debugging tool that accesses the FMC registers directly The following figure indicates the mass erase operation flow Figure 2 2 Process of mass erase operation Set the MER bit Is the LK bit is 0 Send the command to FMC by setting START bit Start Yes No Unlock the FMC_CTL Is the BUSY bit is 0 Yes No Is the BUSY bit i...

Page 36: ...riggered by FMC if the ENDIE bit in the FMC_CTL registers is set Note that the word half word programming operation checks the address if it has been erased If the address has not been erased PGERR bit in the FMC_STAT registers will be set when programming the address except 0x0 Note that the PG bit must be set before the word half word programming operation Additionally the program operation will...

Page 37: ...e the option bytes block in flash The following steps show the erase sequence Unlock the FMC_CTL register if necessary Check the BUSY bit in FMC_STAT register to confirm that no Flash memory operation is in progress BUSY equal to 0 Otherwise wait until the operation has finished Unlock the option bytes operation bits in FMC_CTL register if necessary Wait until OBWEN bit is set in FMC_CTL register ...

Page 38: ...d and verify the Flash memory if required using a DBUS access When the operation is executed successfully the ENDF in FMC_STAT register is set and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set Note that the word half word programming operation checks the address if it has been erased If the address has not been erased PGERR bit in the FMC_STAT register will ...

Page 39: ...nt value bit 15 to 8 0x1fff f80c WP 23 16 Page Erase Program Protection bit 23 to 16 0x1fff f80d WP_N 23 16 WP complement value bit 23 to 16 0x1fff f80e WP 31 24 Page Erase Program Protection bit 31 to 24 WP 30 24 Each bit is related to 4KB flash protection that means 4 pages for GD32VF103 Bit 0 configures the first 4KB flash protection and so on 0x1fff f80f WP_N 31 24 WP complement value bit 31 t...

Page 40: ...t should be followed instead of a system reset if the SPC modification is performed while the debug module is still connected to JTAG device Under the security protection the main flash can only be accessed by user code and the first 4KB flash is under erase program protection In debug mode boot from SRAM or boot from boot loader mode all operations to main flash is forbidden If a read operation t...

Page 41: ... 0 rw Bits Fields Descriptions 31 3 Reserved Must be kept at reset value 2 0 WSCNT 2 0 Wait state counter These bits is set and reset by software The WSCNT valid when WSEN bit in FMC_WSEN is set 000 0 wait state added 001 1 wait state added 010 2 wait state added 011 111 reserved 2 4 2 Unlock key register FMC_KEY Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word ...

Page 42: ...ytes operation unlock key These bits are only be written by software Write OBKEY 31 0 with keys to unlock option bytes command in FMC_CTL register 2 4 4 Status register FMC_STAT Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ENDF WPERR Reserved PGERR ...

Page 43: ...to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ENDIE Reserved ERRIE OBWEN Reserved LK START OBER OBPG Reserved MER PER PG rw rw rw rs rs rw rw rw rw rw Bits Fields Descriptions 31 13 Reserved Must be kept at reset value 12 ENDIE End of operation interrupt enable bit This bit is set or cleared by software 0 no in...

Page 44: ...r clear by software 0 no effect 1 option bytes program command 3 Reserved Must be kept at reset value 2 MER Main flash mass erase for bank0 command bit This bit is set or cleared by software 0 no effect 1 main flash mass erase command for bank0 1 PER Main flash page erase for bank0 command bit This bit is set or clear by software 0 no effect 1 main flash page erase command for bank0 0 PG Main flas...

Page 45: ... 20 19 18 17 16 Reserved DATA 15 6 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA 5 0 USER 7 0 SPC OBERR r r r r Bits Fields Descriptions 31 26 Reserved Must be kept at reset value 25 10 DATA 15 0 Store DATA of option bytes block after system reset 9 2 USER 7 0 Store USER of option bytes block after system reset 1 SPC Option bytes security protection code 0 no protection 1 protection 0 OBERR Option ...

Page 46: ... register FMC_PID Address offset 0x100 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PID 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PID 15 0 r Bits Fields Descriptions 31 0 PID 31 0 Product reserved ID code register 0 These bits are read only by software These bits are unchanged constant after power on These bits are one ...

Page 47: ...The power of the VDD domain is supplied directly by VDD An embedded LDO in the VDD VDDA domain is used to supply the 1 2V domain power A power switch is implemented for the Backup domain It can be powered from the VBAT voltage when the main VDD supply is shut down 3 2 Characteristics Three power domains VBAK VDD VDDA and 1 2V power domains Three power saving modes Sleep Deep sleep and Standby mode...

Page 48: ...supplied by a battery or by another source The power switch is controlled by the Power Down Reset circuit in the VDD VDDA domain If no external battery is used in the application it is recommended to connect VBAT pin externally to VDD pin with a 100nF external ceramic decoupling capacitor The Backup domain reset sources include the Backup domain power on reset BPOR and the Backup Domain software r...

Page 49: ...er domain VDD VDDA domain includes two parts VDD domain and VDDA domain VDD domain includes HXTAL High Speed Crystal oscillator LDO Voltage Regulator POR PDR Power On Down Reset FWDGT Free Watchdog Timer all pads except PC13 PC14 PC15 etc VDDA domain includes ADC DAC AD DA Converter IRC8M Internal 8MHz RC oscillator IRC40K Internal 40KHz RC oscillator PLLs Phase Locking Loop LVD Low Voltage Detect...

Page 50: ..._CS indicates if VDD VDDA is higher or lower than the LVD threshold This event is internally connected to the EXTI line 16 and can generate an interrupt if it is enabled through the EXTI registers Figure 3 3 Waveform of the LVD threshold shows the relationship between the LVD threshold and the LVD output LVD interrupt signal depends on EXTI line 16 rising or falling edge configuration The followin...

Page 51: ...kup domain and the VDD VDDA domain etc are located in this power domain Once the 1 2V is powered up the POR will generate a reset sequence on the 1 2V power domain If need to enter the expected power saving mode the associated control bits must be configured Then once a WFI Wait for Interrupt or WFE Wait for Event instruction is executed the device will enter an expected power saving mode which wi...

Page 52: ...e Standby mode The Standby mode is based on the SLEEPDEEP mode of the RISC V too In Standby mode the whole 1 2V domain is power off the LDO is shut down and all of IRC8M HXTAL and PLLs are disabled Before entering the Standby mode it is necessary to set the CSR_SLEEPVALUE bit in the RISC V System Control Register and set the STBMOD bit in the PMU_CTL register and clear WUF bit in the PMU_CS regist...

Page 53: ...rrupt for WFI Any event or interrupt for WFE WFI Any interrupt from EXTI lines for WFI Any event or interrupt from EXTI for WFE WFI NRST pin WKUP pin FWDGT reset RTC Wakeup Latency None IRC8M wakeup time LDO wakeup time added if LDO is in low power mode Power on sequence ...

Page 54: ...scriptions 31 9 Reserved Must be kept at reset value 8 BKPWEN Backup Domain Write Enable 0 Disable write access to the registers in Backup domain 1 Enable write access to the registers in Backup domain After reset any write access to the registers in Backup domain is ignored This bit has to be set to enable write access to these registers 7 5 LVDT 2 0 Low Voltage Detector Threshold 000 2 2V 001 2 ...

Page 55: ...16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WUPEN Reserved LVDF STBF WUF rw r r r Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 WUPEN WKUP Pin Enable 0 Disable WKUP pin function 1 Enable WKUP pin function If WUPEN is set before entering the power saving mode a rising edge on the WKUP pin wakes up the system from the power saving mode As the WKUP pin is active ...

Page 56: ...red only by a POR PDR or by setting the STBRST bit in the PMU_CTL register 0 WUF Wakeup Flag 0 No wakeup event has been received 1 Wakeup event occurred from the WKUP pin or the RTC wakeup event including RTC Tamper event RTC alarm event or RTC Time Stamp event This bit is cleared only by a POR PDR or by setting the WURST bit in the PMU_CTL register ...

Page 57: ...er and writing access to the registers in Backup domain should be enabled by setting the BKPWEN bit in the PMU_CTL register 4 2 Characteristics 84 bytes Backup registers which can keep data under power saving mode If tamper event is detected Backup registers will be reset The active level of Tamper source PC13 can be configured RTC Clock Calibration register provides RTC alarm and second output se...

Page 58: ...t used for tamper detection signal So the tamper detection configuration should be set before enable TAMPER pin When the tamper event is detected the corresponding TEF bit in the BKP_TPCS register will be set Tamper event can generate an interrupt if tamper interrupt is enabled Any tamper event will reset all Backup data registers Note When TPAL 0 1 if the TAMPER pin is already high low before it ...

Page 59: ...nal output control register BKP_OCTL Address offset 0x2C Reset value 0x0000 bit 6 0 bit 8 bit 9 reset by a Backup domain reset bit 7 reset by a POR PDR This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ROSEL ASOEN COEN RCCV 6 0 rw rw rw rw Bits Fields Descriptions 15 10 Reserved Must be kept at reset value 9 ROSEL RTC output selection 0...

Page 60: ...5 4 3 2 1 0 Reserved TPAL TPEN rw rw Bits Fields Descriptions 15 2 Reserved Must be kept at reset value 1 TPAL TAMPER pin active level 0 The TAMPER pin is active high 1 The TAMPER pin is active low 0 TPEN TAMPER detection enable 0 The TAMPER pin is free for GPIO functions 1 The TAMPER pin is dedicated for the Backup Reset function The active level on the TAMPER pin resets all data of the BKP_DATAx...

Page 61: ... 0 No tamper event occurred 1 A tamper event occurred This bit is reset by writing 1 to the TER bit 7 3 Reserved Must be kept at reset value 2 TPIE Tamper interrupt enable 0 Disable the tamper interrupt 1 Enable the tamper interrupt 1 TIR Tamper interrupt reset 0 No effect 1 Reset the TIF bit This bit is always read as 0 0 TER Tamper event reset 0 No effect 1 Reset the TEF bit This bit is always r...

Page 62: ...andby mode The power reset sets all registers to their reset values except the Backup domain The Power reset whose active signal is low it will be de asserted when the internal LDO voltage regulator is ready to provide 1 2V power The RESET service routine vector is fixed at address 0x0000 0000 in the memory map System reset A system reset is generated by the following events A power reset POWER_RS...

Page 63: ...k Control unit provides a range of frequencies and clock functions These include an Internal 8M RC oscillator IRC8M a High Speed crystal oscillator HXTAL a Low Speed Internal 40K RC oscillator IRC40K a Low Speed crystal oscillator LXTAL three Phase Lock Loop PLL a HXTAL clock monitor clock prescalers clock multiplexers and clock gating circuitry The clocks of the AHB APB and RISC V are derived fro...

Page 64: ...40 KHz IRC40K CK_RTC CK_FWDGT to RTC to FWDGT 128 CK_OUT0 SCS 1 0 RTCSRC 1 0 PREDV0 0 1 CK_PLL CK_HXTAL CK_IRC8M CK_SYS 2 0111 00xx NO CLK 0100 0101 0110 CKOUT0SEL 3 0 48 MHz EXT1 2 1000 1001 1010 CK_PLL1 CK_PLL2 1011 CK_PLL2 1 2 3 15 16 PREDV1 8 9 10 14 16 20 PLL1 PLL1MF PLL2MF 8 9 10 14 16 20 PLL2 CK_PLL1 CK_PLL2 1 2 3 15 16 x2 I2S1 2SEL 0 1 CK_I2S 1 EXT1 to CK_OUT0 PREDV0SEL CK_FMC to FMC The f...

Page 65: ...GT started The FMC is clocked by IRC8M clock which is forced on when IRC8M started 5 2 2 Characteristics 3 to 25 MHz High Speed crystal oscillator HXTAL Internal 8 MHz RC oscillator IRC8M 32 768 Hz Low Speed crystal oscillator LXTAL Internal 40KHz RC oscillator IRC40K PLL clock source can be HXTAL or IRC8M HXTAL clock monitor 5 2 3 Function overview High speed crystal oscillator HXTAL The high spe...

Page 66: ...rrupt can be generated if the related interrupt enable bit IRC8MSTBIE in the Clock Interrupt Register RCU_INT is set when the IRC8M becomes stable The IRC8M clock can also be used as the system clock source or the PLL input clock The frequency accuracy of the IRC8M can be calibrated by the manufacturer but its operating frequency is still less accurate than HXTAL The application requirements envir...

Page 67: ...eal Time Clock circuit or the Free Watchdog Timer The IRC40K offers a low cost clock source as no external components are required The IRC40K RC oscillator can be switched on or off by using the IRC40KEN bit in the Reset source clock Register RCU_RSTSCK The IRC40KSTB flag in the Reset source clock Register RCU_RSTSCK will indicate if the IRC40K clock is stable An interrupt can be generated if the ...

Page 68: ...e RTC clock selection Clock output capability The clock output capability is ranging from 0 09375 MHz to 108 MHz There are several clock signals can be selected via the CK_OUT0 Clock Source Selection bits CKOUT0SEL in the Clock Configuration Register 0 RCU_CFG0 The corresponding GPIO pin should be configured in the properly Alternate Function I O AFIO mode to output the selected clock signal Table...

Page 69: ...ts Fields Descriptions 31 30 Reserved Must be kept at reset value 29 PLL2STB PLL2 Clock Stabilization Flag Set by hardware to indicate if the PLL2 output clock is stable and ready for use 0 PLL2 is not stable 1 PLL2 is stable 28 PLL2EN PLL2 enable Set and reset by software Reset by hardware when entering Deep sleep or Standby mode 0 PLL2 is switched off 1 PLL2 is switched on 27 PLL1STB PLL1 Clock ...

Page 70: ...ntrol bit IRC8MEN state 18 HXTALBPS High speed crystal oscillator HXTAL clock bypass mode enable The HXTALBPS bit can be written only if the HXTALEN is 0 0 Disable the HXTAL Bypass mode 1 Enable the HXTAL Bypass mode in which the HXTAL output clock is equal to the input clock 17 HXTALSTB High speed crystal oscillator HXTAL clock stabilization flag Set by hardware to indicate if the HXTAL oscillato...

Page 71: ... register 0 RCU_CFG0 Address offset 0x04 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PLLMF 4 ADCPSC 2 CKOUT0SEL 3 0 USBFSPSC 1 0 PLLMF 3 0 PREDV0 _LSB PLLSEL rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCPSC 1 0 APB2PSC 2 0 APB1PSC 2 0 AHBPSC 3 0 SCSS 1 0 SCS 1 0 rw rw ...

Page 72: ...requency must not exceed 108 MHz 00000 PLL source clock x 2 00001 PLL source clock x 3 00010 PLL source clock x 4 00011 PLL source clock x 5 00100 PLL source clock x 6 00101 PLL source clock x 7 00110 PLL source clock x 8 00111 PLL source clock x 9 01000 PLL source clock x 10 01001 PLL source clock x 11 01010 PLL source clock x 12 01011 PLL source clock x 13 01100 PLL source clock x 14 01101 PLL s...

Page 73: ...bit 28 of RCU_CFG0 are written by software to define the ADC prescaler factor Set and cleared by software 000 CK_APB2 2 selected 001 CK_APB2 4 selected 010 CK_APB2 6 selected 011 CK_APB2 8 selected 100 CK_APB2 2 selected 101 CK_APB2 12 selected 110 CK_APB2 8 selected 111 CK_APB2 16 selected 13 11 APB2PSC 2 0 APB2 prescaler selection Set and reset by software to control the APB2 clock division rati...

Page 74: ... will be forced to IRC8M when leaving Deep sleep and Standby mode or HXTAL failure is detected by HXTAL clock monitor when HXTAL is selected directly or indirectly as the clock source of CK_SYS 00 select CK_IRC8M as the CK_SYS source 01 select CK_HXTAL as the CK_SYS source 10 select CK_PLL as the CK_SYS source 11 reserved 5 3 3 Clock interrupt register RCU_INT Address offset 0x08 Reset value 0x000...

Page 75: ...Reset PLLSTBIF flag 19 HXTALSTBIC HXTAL Stabilization Interrupt Clear Write 1 by software to reset the HXTALSTBIF flag 0 Not reset HXTALSTBIF flag 1 Reset HXTALSTBIF flag 18 IRC8MSTBIC IRC8M Stabilization Interrupt Clear Write 1 by software to reset the IRC8MSTBIF flag 0 Not reset IRC8MSTBIF flag 1 Reset IRC8MSTBIF flag 17 LXTALSTBIC LXTAL Stabilization Interrupt Clear Write 1 by software to reset...

Page 76: ...rrupt 1 Enable the IRC8M stabilization interrupt 9 LXTALSTBIE LXTAL Stabilization Interrupt Enable LXTAL stabilization interrupt enable disable control 0 Disable the LXTAL stabilization interrupt 1 Enable the LXTAL stabilization interrupt 8 IRC40KSTBIE IRC40K Stabilization interrupt enable IRC40K stabilization interrupt enable disable control 0 Disable the IRC40K stabilization interrupt 1 Enable t...

Page 77: ... the IRC8MSTBIC bit by software 0 No IRC8M stabilization interrupt generated 1 IRC8M stabilization interrupt generated 1 LXTALSTBIF LXTAL stabilization interrupt flag Set by hardware when the Low speed 32 768 Hz crystal oscillator clock is stable and the LXTALSTBIE bit is set Reset when setting the LXTALSTBIC bit by software 0 No LXTAL stabilization interrupt generated 1 LXTAL stabilization interr...

Page 78: ...et by software 0 No reset 1 Reset the SPI0 11 TIMER0RST Timer 0 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER0 10 ADC1RST ADC1 reset This bit is set and reset by software 0 No reset 1 Reset the ADC1 9 ADC0RST ADC0 reset This bit is set and reset by software 0 No reset 1 Reset the ADC0 8 7 Reserved Must be kept at reset value 6 PERST GPIO port E reset This bit is set and ...

Page 79: ...is register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DACRST PMURST BKPIRST CAN1RS T CAN0RS T Reserved I2C1RST I2C0RST UART4R ST UART3R ST USART2 RST USART1 RST Reserved rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI2RST SPI1RST Reserved WWDGT RST Reserved TIMER6R ST TIMER5R ST TIMER4R ST TIME...

Page 80: ...pt at reset value 22 I2C1RST I2C1 reset This bit is set and reset by software 0 No reset 1 Reset the I2C1 21 I2C0RST I2C0 reset This bit is set and reset by software 0 No reset 1 Reset the I2C0 20 UART4RST UART4 reset This bit is set and reset by software 0 No reset 1 Reset the UART4 19 UART3RST UART3 reset This bit is set and reset by software 0 No reset 1 Reset the UART3 18 USART2RST USART2 rese...

Page 81: ... 6 Reserved Must be kept at reset value 5 TIMER6RST TIMER6 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER6 4 TIMER5RST TIMER5 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER5 3 TIMER4RST TIMER4 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER4 2 TIMER3RST TIMER3 reset This bit is set and reset by software 0 No reset 1 Reset...

Page 82: ...ept at reset value 12 USBFSEN USBFS clock enable This bit is set and reset by software 0 Disabled USBFS clock 1 Enabled USBFS clock 11 9 Reserved Must be kept at reset value 8 EXMCEN EXMC clock enable This bit is set and reset by software 0 Disabled EXMC clock 1 Enabled EXMC clock 7 Reserved Must be kept at reset value 6 CRCEN CRC clock enable This bit is set and reset by software 0 Disabled CRC c...

Page 83: ...k 5 3 7 APB2 enable register RCU_APB2EN Address offset 0x18 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved USART0 EN Reserved SPI0EN TIMER0E N ADC1EN ADC0EN Reserved PEEN PDEN PCEN PBEN PAEN Reserved AFEN rw rw rw rw rw rw rw rw rw rw rw Bits...

Page 84: ...port E clock 5 PDEN GPIO port D clock enable This bit is set and reset by software 0 Disabled GPIO port D clock 1 Enabled GPIO port D clock 4 PCEN GPIO port C clock enable This bit is set and reset by software 0 Disabled GPIO port C clock 1 Enabled GPIO port C clock 3 PBEN GPIO port B clock enable This bit is set and reset by software 0 Disabled GPIO port B clock 1 Enabled GPIO port B clock 2 PAEN...

Page 85: ...ts Fields Descriptions 31 30 Reserved Must be kept at reset value 29 DACEN DAC clock enable This bit is set and reset by software 0 Disabled DAC clock 1 Enabled DAC clock 28 PMUEN PMU clock enable This bit is set and reset by software 0 Disabled PMU clock 1 Enabled PMU clock 27 BKPIEN Backup interface clock enable This bit is set and reset by software 0 Disabled Backup interface clock 1 Enabled Ba...

Page 86: ...by software 0 Disabled USART2 clock 1 Enabled USART2 clock 17 USART1EN USART1 clock enable This bit is set and reset by software 0 Disabled USART1 clock 1 Enabled USART1 clock 16 Reserved Must be kept at reset value 15 SPI2EN SPI2 clock enable This bit is set and reset by software 0 Disabled SPI2 clock 1 Enabled SPI2 clock 14 SPI1EN SPI1 clock enable This bit is set and reset by software 0 Disable...

Page 87: ...1 Enabled TIMER2 clock 0 TIMER1EN TIMER1 clock enable This bit is set and reset by software 0 Disabled TIMER1 clock 1 Enabled TIMER1 clock 5 3 9 Backup domain control register RCU_BDCTL Address offset 0x20 Reset value 0x0000 0018 reset by Backup domain Reset This register can be accessed by byte 8 bit half word 16 bit and word 32 bit Note The LXTALEN LXTALBPS RTCSRC and RTCEN bits of the Backup do...

Page 88: ...et 00 No clock selected 01 CK_LXTAL selected as RTC source clock 10 CK_IRC40K selected as RTC source clock 11 CK_HXTAL 128 selected as RTC source clock 7 3 Reserved Must be kept at reset value 2 LXTALBPS LXTAL bypass mode enable Set and reset by software 0 Disable the LXTAL Bypass mode 1 Enable the LXTAL Bypass mode 1 LXTALSTB Low speed crystal oscillator stabilization flag Set by hardware to indi...

Page 89: ...imer reset generated Reset by writing 1 to the RSTFC bit 0 No window watchdog reset generated 1 Window watchdog reset generated 29 FWDGTRSTF Free watchdog timer reset flag Set by hardware when a free watchdog timer reset generated Reset by writing 1 to the RSTFC bit 0 No free watchdog timer reset generated 1 free Watchdog timer reset generated 28 SWRSTF Software reset flag Set by hardware when a s...

Page 90: ...ot stable 1 IRC40K is stable 0 IRC40KEN IRC40K enable Set and reset by software 0 Disable IRC40K 1 Enable IRC40K 5 3 11 AHB reset register RCU_AHBRST Address offset 0x28 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved USBFSR ST Reserved rw Bit...

Page 91: ... I2S2 source clock 1 CK_PLL2 x 2 selected as I2S2 source clock 17 I2S1SEL I2S1 Clock Source Selection Set and reset by software to control the I2S1 clock source 0 System clock selected as I2S1 source clock 1 CK_PLL2 x 2 selected as I2S1 source clock 16 PREDV0SEL PREDV0 input Clock Source Selection Set and reset by software 0 HXTAL selected as PREDV0 input source clock 1 CK_PLL1 selected as PREDV0 ...

Page 92: ...00 PREDV1 input source clock divided by 5 0101 PREDV1 input source clock divided by 6 0110 PREDV1 input source clock divided by 7 0111 PREDV1 input source clock divided by 8 1000 PREDV1 input source clock divided by 9 1001 PREDV1 input source clock divided by 10 1010 PREDV1 input source clock divided by 11 1011 PREDV1 input source clock divided by 12 1100 PREDV1 input source clock divided by 13 11...

Page 93: ...e clock divided by 15 1111 PREDV0 input source clock divided by 16 5 3 13 Deep sleep mode voltage register RCU_DSV Address offset 0x34 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DSLPVS 1 0 rw Bits Fields Descriptions 31 2 Reserved Must be...

Page 94: ...about ECLIC EXTI interrupt event controller contains up to 19 independent edge detectors and generates interrupt requests or events to the processer The EXTI has three trigger types rising edge falling edge and both edges Each edge detector in the EXTI can be configured and masked independently 6 2 Characteristics Up to 68 maskable peripheral interrupts 4 bits interrupt priority configuration 16 p...

Page 95: ...MA0 channel2 global interrupt 0x0000_0080 33 DMA0 channel3 global interrupt 0x0000_0084 34 DMA0 channel4 global interrupt 0x0000_0088 35 DMA0 channel5 global interrupt 0x0000_008C 36 DMA0 channel6 global interrupt 0x0000_0090 37 ADC0 and ADC1 global interrupt 0x0000_0094 38 CAN0 TX interrupts 0x0000_0098 39 CAN0 RX0 interrupts 0x0000_009C 40 CAN0 RX1 interrupts 0x0000_00A0 41 CAN0 EWMC interrupts ...

Page 96: ...Reserved 0x0000_010C 68 Reserved 0x0000_0110 69 TIMER4 global interrupt 0x0000_0114 70 SPI2 global interrupt 0x0000_0118 71 UART3 global interrupt 0x0000_011C 72 UART4 global interrupt 0x0000_0120 73 TIMER5 global interrupt 0x0000_0124 74 TIMER6 global interrupt 0x0000_0128 75 DMA1 channel0 global interrupt 0x0000_012C 76 DMA1 channel1 global interrupt 0x0000_0130 77 DMA1 channel2 global interrupt...

Page 97: ...dge detector in the EXTI can be configured and masked independently The EXTI trigger source includes 16 external lines from GPIO pins and 3 lines from internal modules including LVD RTC Alarm USB Wakeup All GPIO pins can be selected as an EXTI trigger source by configuring AFIO_EXTISSx registers in GPIO module please refer to GPIO and AFIO section for detail EXTI can provide not only interrupts bu...

Page 98: ...3 PC3 PD3 PE3 4 PA4 PB4 PC4 PD4 PE4 5 PA5 PB5 PC5 PD5 PE5 6 PA6 PB6 PC6 PD6 PE6 7 PA7 PB7 PC7 PD7 PE7 8 PA8 PB8 PC8 PD8 PE8 9 PA9 PB9 PC9 PD9 PE9 10 PA10 PB10 PC10 PD10 PE10 11 PA11 PB11 PC11 PD11 PE11 12 PA12 PB12 PC12 PD12 PE12 13 PA13 PB13 PC13 PD13 PE13 14 PA14 PB14 PC14 PD14 PE14 15 PA15 PB15 PC15 PD15 PE15 16 LVD 17 RTC Alarm 18 USB Wakeup ...

Page 99: ... rw Bits Fields Descriptions 31 19 Reserved Must be kept at reset value 18 0 INTENx Interrupt enable bit 0 Interrupt from Linex is disabled 1 Interrupt from Linex is enabled 6 6 2 Event enable register EXTI_EVEN Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved EVEN18 EVEN17 EVEN16 rw rw rw 15 14 13 ...

Page 100: ...ENx Rising edge trigger enable 0 Rising edge of Linex is invalid 1 Rising edge of Linex is valid as an interrupt event request 6 6 4 Falling edge trigger enable register EXTI_FTEN Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FTEN18 FTEN17 FTEN16 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FTE...

Page 101: ...pt Event software trigger 0 Deactivate the EXTIx software interrupt event request 1 Activate the EXTIx software interrupt event request 6 6 6 Pending register EXTI_PD Address offset 0x14 Reset value undefined This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PD18 PD17 PD16 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 ...

Page 102: ...oftware as output push pull or open drain input peripheral alternate function or analog mode Each GPIO pin can be configured as pull up pull down or no pull up pull down All GPIOs are high current capable except for analog mode 7 2 Characteristics Input output direction control Schmitt trigger input function enable control Each pin weak pull up pull down function Output push pull open drain enable...

Page 103: ...ture of a standard I O port bit Vss Output Control Vdd Output Control Register Input Status Register Write Read Write Alternate Function Output Read Alternate Function Input Analog Input Output Input driver Output driver I O pin Schmitt trigger Bit Operate Registers ESD protection Vdd Vss 7 3 1 GPIO pin configuration During or just after the reset period the alternative functions are all inactive ...

Page 104: ...to the bit operate register GPIOx_BOP or for clearing only GPIOx_BC The other bits will not be affected 7 3 2 External interrupt event lines All ports have external interrupt capability To use external interrupt lines the port must be configured in input mode 7 3 3 Alternate functions AF When the port is configured as AFIO set CTLy bits to 0b10 or 0b11 and set MDy bits to 0b01 0b10 or 0b11 which i...

Page 105: ... 1 in the output control register Push Pull Mode The pad output low level when a 0 in the output control register while the pad output high level when a 1 in the output control register A read access to the port output control register gets the last written value A read access to the port input status register gets the I O state Figure 7 3 Output configuration shows the output configuration Figure...

Page 106: ...the GPIO supports some alternate functions mapped to some other pins by software When be configured as alternate function The output buffer is enabled in Open Drain or Push Pull configuration The output buffer is driven by the peripheral The schmitt trigger input is enabled The weak pull up and pull down resistors could be chosen when input The I O pin data is stored into the port input status reg...

Page 107: ... used for AF input function by configuring MDy bits to 0b00 in GPIOx_CTL0 GPIOx_CTL1 registers And set output function by configuring MDy bits to 0b01 0b10 or 0b11 and configuring CTLy bits of corresponding port in GPIOx_CTL0 GPIOx_CTL1 register to 0b10 for AF push pull output or 0b11 for AF open drain output 7 3 9 GPIO locking function The locking mechanism allows the IO configuration to be prote...

Page 108: ...rupt or event 7 4 2 Main features APB slave interface for register access EXTI source selection Each pin has up to four alternative functions for configuration 7 4 3 JTAG alternate function remapping The debug interface signals are mapped on the GPIO ports as shown in table below Table 7 2 Debug interface signals Alternate function GPIO port JTMS PA13 JTCK PA14 JTDI PA15 JTDO PB3 NJTRST PB4 To red...

Page 109: ... remap TIMER1_REMAP 1 0 01 partial remap TIMER1_REMAP 1 0 10 partial remap TIMER1_REMAP 1 0 11 full remap 2 TIMER1_CH0 TIMER 1_ETI 1 PA0 PA15 PA0 PA15 TIMER1_CH1 PA1 PB3 PA1 PB3 TIMER1_CH2 PA2 PB10 TIMER1_CH3 PA3 PB11 1 For different packages and flash sizes please refer to the datasheet Table 7 6 TIMER2 alternate function remapping Alternate function TIMER2_REMAP 1 0 00 no remap TIMER2_REMAP 1 0 ...

Page 110: ...USART0_TX PA9 PB6 USART0_RX PA10 PB7 Table 7 10 USART1 alternate function remapping Alternate function USART1_REMAP 0 USART1_REMAP 1 2 USART1_CTS PA0 PD3 USART1_RTS PA1 PD4 USART1_TX PA2 PD5 USART1_RX PA3 PD6 USART1_CK PA4 PD7 Table 7 11 USART2 alternate function remapping Alternate function USART2_REMAP 1 0 00 no remap USART2_REMAP 1 0 01 partial remap 1 USART2_REMAP 1 0 11 full remap 2 USART2_TX...

Page 111: ...MAP 1 SPI2_NSS I2S2_WS PA15 PA4 SPI2_SCK I2S2_CK PB3 PC10 SPI2_MISO PB4 PC11 SPI2_MOSI I2S2_SD PB5 PC12 7 4 9 CAN0 AF remapping Refer to AFIO port configuration register 0 AFIO_ PCF0 Table 7 15 CAN0 alternate function remapping Alternate function CAN0_REMAP 1 0 00 CAN0_REMAP 1 0 10 2 CAN0_REMAP 1 0 11 1 CAN0_RX PA11 PB8 PD0 CAN0_TX PA12 PB9 PD1 1 This remapping is available only on 100 pin package...

Page 112: ...by VBAT VDD no more supplied the PC14 PC15 GPIO functionality is lost and will be set in analog mode 2 Refer to the note on IO usage restrictions in Section Battery backup domain Table 7 17 OSC32 pins configuration Alternate function LXTAL ON LXTAL OFF PC14 OSC32_IN PC14 PC15 OSC32_OUT PC15 The HXTAL oscillator pins OSC_IN OSC_OUT can be used as general purpose I O PD0 PD1 Table 7 18 OSC pins conf...

Page 113: ...3 2 1 0 CTL3 1 0 MD3 1 0 CTL2 1 0 MD2 1 0 CTL1 1 0 MD1 1 0 CTL0 1 0 MD0 1 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 CTL7 1 0 Port 7 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 29 28 MD7 1 0 Port 7 mode bits These bits are set and cleared by software refer to MD0 1 0 description 27 26 CTL6 1 0 Port 6 configuration bits These bits are se...

Page 114: ...e bits are set and cleared by software refer to CTL0 1 0 description 9 8 MD2 1 0 Port 2 mode bits These bits are set and cleared by software refer to MD0 1 0 description 7 6 CTL1 1 0 Port 1 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 5 4 MD1 1 0 Port 1 mode bits These bits are set and cleared by software refer to MD0 1 0 description 3 2 CTL0 1 0 Port...

Page 115: ... rw rw rw rw rw rw Bits Fields Descriptions 31 30 CTL15 1 0 Port 15 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 29 28 MD15 1 0 Port 15 mode bits These bits are set and cleared by software refer to MD0 1 0 description 27 26 CTL14 1 0 Port 14 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 25 24 MD14 1 0 Port...

Page 116: ...ese bits are set and cleared by software refer to MD0 1 0 description 7 6 CTL9 1 0 Port 9 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 5 4 MD9 1 0 Port 9 mode bits These bits are set and cleared by software refer to MD0 1 0 description 3 2 CTL8 1 0 Port 8 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 1 0 M...

Page 117: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OCTL15 OCTL14 OCTL13 OCTL12 OCTL11 OCTL10 OCTL9 OCTL8 OCTL7 OCTL6 OCTL5 OCTL4 OCTL3 OCTL2 OCTL1 OCTL0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 OCTLy Port output control y 0 15 These bits are set and cleared by software 0 Pin output low 1 Pin output high 7 5 5 Port bit operate register G...

Page 118: ...as to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 w w w w w w w w w w w w w w w w Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CRy Port Clear bit y y 0 15 These bits are set and cleared by software 0 No action on the corresp...

Page 119: ...ts are set and cleared by software 0 The corresponding bit port configuration is not locked 1 The corresponding bit port configuration is locked when LKK bit is 1 7 5 8 Event control register AFIO_EC Address offset 0x00 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EOE ...

Page 120: ... 10 9 8 7 6 5 4 3 2 1 0 PD01_RE MAP CAN0_REMAP 1 0 TIMER3_ REMAP TIMER2_REMAP 1 0 TIMER1_REMAP 1 0 TIMER0_REMAP 1 0 USART2_REMAP 1 0 USART1_ REMAP USART0_ REMAP I2C0_RE MAP SPI0_RE MAP rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 28 Reserved Must be kept at reset value 29 TIMER1ITI1_REMAP TIMER1 internal trigger 1 remapping These bits are set and cleared by software It control the ...

Page 121: ...erved Must be kept at reset value 16 TIMER4CH3_IREMA P TIMER4 channel3 internal remapping Set and cleared by software This bit controls the TIMER4_CH3 internal mapping When reset the timer TIMER4_CH3 is connected to PA3 When set the IRC40K internal clock is connected to TIMER4_CH3 input for calibration purpose Note This bit is available only in High density value line devices 15 PD01_REMAP Port D0...

Page 122: ...ed by software 00 No remap TIMER0_ETI PA12 TIMER0_CH0 PA8 TIMER0_CH1 PA9 TIMER0_CH2 PA10 TIMER0_CH3 PA11 TIMER0_BKIN PB12 TIMER0_CH0_ON PB13 TIMER0_CH1_ON PB14 TIMER0_CH2_ON PB15 01 Partial remap TIMER0_ETI PA12 TIMER0_CH0 PA8 TIMER0_CH1 PA9 TIMER0_CH2 PA10 TIMER0_CH3 PA11 TIMER0_BKIN PA6 TIMER0_CH0_ON PA7 TIMER0_CH1_ON PB0 TIMER0_CH2_ON PB1 10 Not used 11 Full remap TIMER0_ETI PE7 TIMER0_CH0 PE9 ...

Page 123: ...e 0 No remap SPI0_NSS PA4 SPI0_SCK PA5 SPI0_MISO PA6 SPI0_MOSI PA7 1 Remap SPI0_NSS PA15 SPI0_SCK PB3 SPI0_MISO PB4 SPI0_MOSI PB5 7 5 10 EXTI sources selection register 0 AFIO_EXTISS0 Address offset 0x08 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI3_SS 3 0 EXTI2_SS 3 0 EXT...

Page 124: ...pin 0011 PD0 pin 0100 PE0 pin Other configurations are reserved 7 5 11 EXTI sources selection register 1 AFIO_EXTISS1 Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI7_SS 3 0 EXTI6_SS 3 0 EXTI5_SS 3 0 EXTI4_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 ...

Page 125: ...4 sources selection 0000 PA4 pin 0001 PB4 pin 0010 PC4 pin 0011 PD4 pin 0100 PE4 pin Other configurations are reserved 7 5 12 EXTI sources selection register 2 AFIO_EXTISS2 Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI11_SS 3 0 EXTI10_SS 3 0 EXTI9_SS 3 0...

Page 126: ...pin Other configurations are reserved 3 0 EXTI8_SS 3 0 EXTI 8 sources selection 0000 PA8 pin 0001 PB8 pin 0010 PC8 pin 0011 PD8 pin 0100 PE8 pin Other configurations are reserved 7 5 13 EXTI sources selection register 3 AFIO_EXTISS3 Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 ...

Page 127: ...TI 13 sources selection 0000 PA13 pin 0001 PB13 pin 0010 PC13 pin 0011 PD13 pin 0100 PE13 pin Other configurations are reserved 3 0 EXTI12_SS 3 0 EXTI 12 sources selection 0000 PA12 pin 0001 PB12 pin 0010 PC12 pin 0011 PD12 pin 0100 PE12 pin Other configurations are reserved 7 5 14 AFIO port configuration register 1 AFIO_PCF1 Address offset 0x1C Reset value 0x0000 0000 This register has to be acce...

Page 128: ...MC_NADV EXMC_NADV connect disconnect This bit is set and cleared by software it controls the use of optional EXMC_NADV signal 0 The NADV signal is connected to the output default 1 The NADV signal is not connected The I O pin can be used by another peripheral 9 0 Reserved Must be kept at reset value ...

Page 129: ... 4 AHB clock cycles for 32 bit input data size from data entered to the calculation result available Free 8 bit register is unrelated to calculation and can be used for any other goals by any other peripheral devices Fixed polynomial 0x4C11DB7 X32 X26 X23 X22 X16 X12 X11 X10 X8 X7 X5 X4 X2 X 1 This 32 bit CRC polynomial is a common polynomial used in Ethernet Figure 8 1 Block diagram of CRC calcul...

Page 130: ...software setting the CRC_CTL register the new input raw data will be calculated based on the result of previous value of CRC_DATA CRC calculation will spend 4 AHB clock cycles for 32 bit data size during this period AHB will not be hanged because of the existence of the 32 bit input buffer This module supplies an 8 bit free register CRC_FDATA CRC_FDATA is unrelated to the CRC calculation any value...

Page 131: ...tware writes and reads This register is used to calculate new data and the register can be written the new data directly Written value cannot be read because the read value is the previous CRC calculation result 8 4 2 Free data register CRC_FDATA Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 1...

Page 132: ... value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RST rs Bits Fields Descriptions 31 1 Reserved Must be kept at reset value 0 RST Set this bit can reset the CRC_DATA register to the value of 0xFFFFFFFF then automatically cleared itself to 0 by hardware This bit will take no effe...

Page 133: ...CPU access to the system bus for some bus cycles Round robin scheduling is implemented in the bus matrix to ensure at least half of the system bus bandwidth for the CPU 9 2 Characteristics Programmable length of data to be transferred max to 65536 12 channels and each channel are configurable 7 for DMA0 and 5 for DMA1 AHB and APB peripherals FLASH SRAM can be accessed as source and destination Eac...

Page 134: ...quests coming at the same time Channel management to control address data selection and data counting 9 4 Function overview 9 4 1 DMA operation Each DMA transfer consists of two operations including the loading of data from the source and the storage of the loaded data to the destination The source and destination addresses are computed by the DMA controller based on the programmed values in the D...

Page 135: ... bits 16 bits 1 Read B1B0 15 0 0x0 2 Read B3B2 15 0 0x2 3 Read B5B4 15 0 0x4 4 Read B7B6 15 0 0x6 1 Write B1B0 15 0 0x0 2 Write B3B2 15 0 0x2 3 Write B5B4 15 0 0x4 4 Write B7B6 15 0 0x6 16 bits 8 bits 1 Read B1B0 15 0 0x0 2 Read B3B2 15 0 0x2 3 Read B5B4 15 0 0x4 4 Read B7B6 15 0 0x6 1 Write B0 7 0 0x0 2 Write B2 7 0 0x1 3 Write B4 7 0 0x2 4 Write B6 7 0 0x3 8 bits 32 bits 1 Read B0 7 0 0x0 2 Read...

Page 136: ...ting that the DMA controller has initiated an AHB command to access the peripheral Figure 9 2 Handshake mechanism shows how the handshake mechanism works between the DMA controller and peripherals Figure 9 2 Handshake mechanism DMA Acknowledge Peripheral request Peripheral is ready to transmit or receive data and assert the request signal to DMA Peripheral request Peripheral request DMA acknowledg...

Page 137: ...reloaded with the pre programmed value and the full transfer finish flag is asserted at the end of every DMA transfer DMA can always responds the peripheral request until the CHEN bit in the DMA_CHxCTL register is cleared 9 4 6 Memory to memory mode The memory to memory mode is enabled by setting the M2M bit in the DMA_CHxCTL register In this mode the DMA channel can also work without being trigge...

Page 138: ...ee types of interrupt event including full transfer finish half transfer finish and transfer error Each interrupt event has a dedicated flag bit in the DMA_INTF register a dedicated clear bit in the DMA_INTC register and a dedicated enable bit in the DMA_CHxCTL register The relationship is described in the following Table 9 2 Interrupt events Table 9 2 Interrupt events Interrupt event Flag bit Cle...

Page 139: ...each channel of DMA0 and Table 9 4 DMA1 requests for each channel lists the support request from peripheral for each channel of DMA1 Figure 9 4 DMA0 request mapping ADC0 TIMER1_CH2 TIMER3_CH0 or or Channel 0 MEMTOMEM0 Hardware priority high low SPI0_RX USART2_TX TIMER0_CH0 TIMER1_UP TIMER2_CH2 or or Channel 1 MEMTOMEM2 MEMTOMEM1 SPI0_TX USART2_RX TIMER0_CH1 TIMER2_CH3 TIMER2_UP or or Channel 2 MEM...

Page 140: ... TIMER3_CH0 TIMER3_CH1 TIMER3_CH2 TIMER3_UP ADC0 ADC0 SPI I2S SPI0_RX SPI0_TX SPI1 I2S1_R X SPI1 I2S1_T X USART USART2_TX USART2_RX USART0_TX USART0_RX USART1_RX USART1_TX I2C I2C1_TX I2C1_RX I2C0_TX I2C0_RX Figure 9 5 DMA1 request mapping SPI2 I2S2_RX TIMER4_CH3 TIMER4_TG or or Channel 0 MEMTOMEM0 Hardware priority high low SPI2 I2S2_TX TIMER4_CH2 TIMER4_UP or or Channel 1 MEMTOMEM2 MEMTOMEM1 UAR...

Page 141: ...each channel Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 TIMER4 TIMER4_CH3 TIMER4_TG TIMER4_CH2 TIMER4_UP TIMER4_CH1 TIMER4_CH0 TIMER5 TIMER5_UP TIMER6 TIMER6_UP DAC DAC_CH0 DAC_CH1 SPI I2S SPI2 I2S2_RX SPI2 I2S2_TX USART UART3_RX UART3_TX ...

Page 142: ... Must be kept at reset value 27 23 19 15 11 7 3 ERRIFx Error flag of channel x x 0 6 Hardware set and software cleared by configuring DMA_INTC register 0 Transfer error has not occurred on channel x 1 Transfer error has occurred on channel x 26 22 18 14 10 6 2 HTFIFx Half transfer finish flag of channel x x 0 6 Hardware set and software cleared by configuring DMA_INTC register 0 Half number of tra...

Page 143: ...error flag of channel x x 0 6 0 No effect 1 Clear error flag 26 22 18 14 10 6 2 HTFIFCx Clear bit for half transfer finish flag of channel x x 0 6 0 No effect 1 Clear half transfer finish flag 25 21 17 13 9 5 1 FTFIFCx Clear bit for full transfer finish flag of channel x x 0 6 0 No effect 1 Clear full transfer finish flag 24 20 16 12 8 4 0 GIFCx Clear global interrupt flag of channel x x 0 6 0 No ...

Page 144: ...H 1 0 Transfer data size of memory Software set and cleared 00 8 bit 01 16 bit 10 32 bit 11 Reserved These bits can not be written when CHEN is 1 9 8 PWIDTH 1 0 Transfer data size of peripheral Software set and cleared 00 8 bit 01 16 bit 10 32 bit 11 Reserved These bits can not be written when CHEN is 1 7 MNAGA Next address generation algorithm of memory Software set and cleared 0 Fixed address mo...

Page 145: ... for channel half transfer finish interrupt Software set and cleared 0 Disable channel half transfer finish interrupt 1 Enable channel half transfer finish interrupt 1 FTFIE Enable bit for channel full transfer finish interrupt Software set and cleared 0 Disable channel full transfer finish interrupt 1 Enable channel full transfer finish interrupt 0 CHEN Channel enable Software set and cleared 0 D...

Page 146: ...egister DMA_CHxPADDR x 0 6 where x is a channel number Address offset 0x10 0x14 x Reset value 0x0000 0000 This register has to be accessed by word 32 bit Note Do not configure this register when channel is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PADDR 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PADDR 15 0 rw Bits Fields Descriptions 31 0 PADDR 31 0 Peripheral base address These ...

Page 147: ... 1 0 MADDR 15 0 rw Bits Fields Descriptions 31 0 MADDR 31 0 Memory base address These bits can not be written when CHEN in the DMA_CHxCTL register is 1 When MWIDTH in the DMA_CHxCTL register is 01 16 bit the LSB of these bits is ignored Access is automatically aligned to a half word address When MWIDTH in the DMA_CHxCTL register is 10 32 bit the two LSBs of these bits are ignored Access is automat...

Page 148: ...rview Debug capabilities can be accessed by a debug tool via JTAG interface JTAG Debug Port 10 2 1 Pin assignment The JTAG interface provides 5 pin standard JTAG known as JTAG clock JTCK JTAG mode selection JTMS JTAG data input JTDI JTAG data output JTDO and JTAG reset NJTRST active low The pin assignment are PA15 JTDI PA14 JTCK PA13 JTMS PB4 NJTRST PB3 JTDO By default 5 pin standard JTAG debug mo...

Page 149: ...ck are provided by CK_IRC8M and the debugger can debug in standby mode When exit the standby mode a system reset generated When DSLP_HOLD bit in DBG control register DBG_CTL is set and entering the Deep sleep mode the clock of AHB bus and system clock are provided by CK_IRC8M and the debugger can debug in Deep sleep mode When SLP_HOLD bit in DBG control register DBG_CTL is set and entering the sle...

Page 150: ...0 4 2 Control register DBG_CTL Address offset 0x04 Reset value 0x0000 0000 power reset only This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved CAN1_H OLD TIMER6_ HOLD TIMER5_ HOLD TIMER4_ HOLD Reserved I2C1_HO LD rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2C0_HO LD CAN0_H OLD TIMER3_ HOLD TIMER2_ HOLD TIMER1_ HOLD TIMER0_ HOLD WWDGT_...

Page 151: ... set and reset by software 0 no effect 1 hold the I2C1 SMBUS timeout for debug when core halted 15 I2C0_HOLD I2C0 hold bit This bit is set and reset by software 0 no effect 1 hold the I2C0 SMBUS timeout for debug when core halted 14 CAN0_HOLD CAN0 hold bit This bit is set and reset by software 0 no effect 1 the receive register of CAN0 stops receiving data when core halted 13 TIMER3_HOLD TIMER 3 h...

Page 152: ...clock for debug when core halted 7 3 Reserved Must be kept at reset value 2 STB_HOLD Standby mode hold register This bit is set and reset by software 0 no effect 1 At the standby mode the clock of AHB bus and system clock are provided by CK_IRC8M a system reset generated when exit standby mode 1 DSLP_HOLD Deep sleep mode hold register This bit is set and reset by software 0 no effect 1 At the Deep...

Page 153: ...ding the related computational burden from the MCU 11 2 Main features High performance 12 bit 10 bit 8 bit or 6 bit configurable resolution ADC sampling rate 2 MSPs for 12 bit resolution Self calibration Programmable sampling time Data alignment with built in data coherency DMA support Analog input channels 16 external analog inputs 1 channel for internal temperature sensor VSENSE 1 channel for in...

Page 154: ...ription VSENSE Input Internal temperature sensor output voltage VREFINT Input Internal voltage reference output voltage Table 11 2 ADC pins definition Name Signal type Remarks VDDA Input analog power supply Analog power supply equal to VDD and 2 6 V VDDA 3 6 V VSSA Input analog power supply ground Ground for analog power supply equal to VSS VREF Input positive reference voltage The positive refere...

Page 155: ...tes a calibration factor which is internally applied to the ADC until the next ADC power off The application must not use the ADC during calibration and must wait until it is completed Calibration should be performed before starting A D conversion The calibration is initiated by software by setting bit CLB 1 CLB bit stays at 1 during all the calibration sequence It is then cleared by hardware as s...

Page 156: ..._RSQ0 register specify the total conversion sequence length In the inserted group a sequence of up to 4 conversions can be organized in a specific sequence The ADC_ISQ register specify the selected channels of the inserted group The IL 1 0 bits in the ADC_ISQ register specify the total conversion sequence length 11 4 5 Conversion modes Single conversion mode This mode can be running on both regula...

Page 157: ...ADC_SAMPTx register 4 Configure ETEIC and ETSIC bits in the ADC_CTL1 register if in need 5 Set the SWICST bit or generate an external trigger for the inserted group 6 Wait the EOC EOIC flags to be set 7 Read the converted in the ADC_IDATA0 register 8 Clear the EOC EOIC flags by writing 0 to them Continuous conversion mode This mode can be run on the regular channel group The continuous conversion ...

Page 158: ... or ADC_ISQ register When the ADCON has been set high the ADC samples and converts specified channels one by one in the regular or inserted group till the end of the regular or inserted group once the corresponding software trigger or external trigger is active The conversion data will be stored in the ADC_RDATA or ADC_IDATAx register After conversion of the regular or inserted channel group the E...

Page 159: ...erforms a short sequence of n conversions n 8 which is a part of the sequence of conversions selected in the ADC_RSQ0 ADC_RSQ2 registers The value of n is defined by the DISNUM 2 0 bits in the ADC_CTL0 register When the corresponding software trigger or external trigger is active the ADC samples and coverts the next n channels selected in the ADC_RSQ0 ADC_RSQ2 registers until all the channels in t...

Page 160: ...e set 9 Clear the EOC flag by writing 0 to it Software procedure for discontinuous conversion on an inserted channel group 1 Set the DISIC bit in the ADC_CTL0 register 2 Configure ADC_ISQ and ADC_SAMPTx registers 3 Configure ETEIC and ETSIC bits in the ADC_CTL1 register if in need 4 Set the SWICST bit or generate an external trigger for the inserted group 5 Repeat step4 if in need 6 Wait the EOC E...

Page 161: ...rted group Analog watchdog The analog watchdog is enabled when the RWDEN and IWDEN bits in the ADC_CTL0 register are set for regular and inserted channel groups respectively When the analog voltage converted by the ADC is below a low threshold or above a high threshold the WDE bit in ADC_STAT register will be set An interrupt will be generated if the WDEIE bit is set The ADC_WDHT and ADC_WDLT regi...

Page 162: ... 11 10 6 bit Data alignment Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 D5 D4 D3 D2 D1 D0 Regular group data Inserted group data D1 D0 0 Sign Sign Sign Sign Sign Sign Sign Sign Sign D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 D5 D4 D2 Regular group data Inserted group data DAL 0 DAL 1 D3 11 4 8 Programmable sample time The number of ADCCLK cycles which is used...

Page 163: ... EXTI11 External signal 111 SWRCST Software trigger Table 11 4 External trigger for inserted channels for ADC0 and ADC1 ETSIC 2 0 Trigger Source Trigger Type 000 TIMER0_TRGO Internal on chip signal 001 TIMER0_CH3 010 TIMER1_TRGO 011 TIMER1_CH0 100 TIMER2_CH3 101 TIMER3_TRGO 110 EXTI15 External signal 111 SWICST Software trigger 11 4 10 DMA request The DMA request which is enabled by the DMA bit of...

Page 164: ...control register 1 ADC_CTL1 3 Start the ADC conversion by setting the ADCON bit or by external trigger 4 Read the resulting temperature data Vtemperature in the ADC data register and get the temperature using the following formula Temperature C V25 Vtemperature digit Avg_Slope 25 V25 Vtemperature value at 25 C the typical value please refer to the datasheet Avg_Slope Average Slope for curve betwee...

Page 165: ...rsampling ratio N is defined by the OVSR 2 0 bits in the ADC_OVSAMPCTL register It can range from 2x to 256x The division coefficient M means bit right shifting up to 8 bit It is configured through the OVSS 3 0 bits in the ADC_OVSAMPCTL register The summation unit can yield a result up to 20 bits 256 x 12 bit which is first shifted right The upper bits of the result are then truncated keeping only...

Page 166: ... devices with two ADC ADC sync mode can be used In ADC sync mode the conversion starts alternately or simultaneously triggered by ADC0 master to ADC1 slave according to the mode selected by the SYNCM 3 0 bits in ADC1_CTL0 register Oversa mpling ratio Max Raw data No shift OVSS 0000 1 bit shift OVSS 0001 2 bit shift OVSS 0010 3 bit shift OVSS 0011 4 bit shift OVSS 0100 5 bit shift OVSS 0101 6 bit s...

Page 167: ...de trigger rotation mode Inserted parallel mode follow up fast mode Inserted parallel mode follow up slow mode In ADC sync mode the DMA bit must be set even if it is not used the converted data of ADC slave can be read from the master data register Figure 11 13 ADC sync block diagram ADC_IN0 ADC_IN1 ADC_IN15 GPIO VSENSE VREF EXTI11 EXTI15 A P B B U S ADC0 master ADC1 slave Regular data registers 1...

Page 168: ...ime should be configured for the two channels that will be sampled simultaneously by ACD0 and ADC1 Figure 11 14 Regular parallel mode on 16 channels CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 ADC0 ADC1 Regular trigger CH14 CH2 Sample Convert CH15 CH3 CH0 CH4 CH1 CH5 EOC 11 6 2 Inserted parallel mode This mode converts the inserted channel simultaneously The source of external trigger comes from the inserted ...

Page 169: ...uous conversion mode After an EOC interrupt is generated by ADC0 in case of setting the EOCIE bit we can use a 32 bit DMA which transfers to SRAM the ADC_RDATA 32 bit register containing the ADC1 converted data in the upper half word and the ADC0 converted data in the lower half word Note The maximum sampling time allowed is 7 ADCCLK cycles to avoid the overlap between ADC0 and ADC1 sampling phase...

Page 170: ...ernal trigger for inserted channel occurs Figure 11 17 Follow up slow mode on 1 channel CH1 ADC0 ADC1 Regular trigger Sample Convert EOC ADC0 EOC ADC1 CH1 CH1 CH1 CH1 CH1 CH1 CH1 14 ADCCLK cycles 14 ADCCLK cycles 11 6 5 Trigger rotation mode This mode can be running on the inserted channel group The source of external trigger comes from the inserted channel MUX of ADC0 selected by the ETSIC 2 0 bi...

Page 171: ...terrupt occurred If another external trigger occurs after all inserted group channels have been converted then the trigger rotation process restarts Figure 11 19 Trigger rotation inserted channels in discontinuous mode Inserted trigger CH4 CH5 EOIC ADC0 Sample Convert CH0 CH1 ADC0 ADC1 EOIC ADC1 CH2 CH6 CH3 CH7 11 6 6 Combined regular parallel inserted parallel mode In the free mode the conversion...

Page 172: ...ed trigger Sample Convert CH15 CH14 If one inserted trigger occurs during an inserted conversion that has interrupted a regular conversion it will be ignored Figure 11 21 Trigger occurs during inserted conversion shows the case the third trigger is ignored Figure 11 21 Trigger occurs during inserted conversion CH0 CH1 CH1 CH2 CH3 CH3 CH4 CH5 CH4 CH5 CH5 CH6 CH7 CH7 CH8 CH9 ADC0 ADC1 Inserted trigg...

Page 173: ...serted trigger Sample Convert CH0 CH0 CH0 ADC1 regular ADC1 inserted 11 7 ADC interrupts The interrupt can be produced on one of the events End of conversion for regular and inserted groups The analog watchdog event Separate interrupt enable bits are available for flexibility The interrupts of ADC0 ADC1 are mapped into the same interrupt vector ISR 18 ...

Page 174: ...rted 1 Regular channel group started Set by hardware when regular channel conversion starts Cleared by software writing 0 to it 3 STIC Start flag of inserted channel group 0 No inserted channel group started 1 Inserted channel group started Set by hardware when inserted channel group conversion starts Cleared by software writing 0 to it 2 EOIC End of inserted group conversion flag 0 No end of inse...

Page 175: ...WDCHSEL 4 0 rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 RWDEN Regular channel analog watchdog enable 0 Regular channel analog watchdog disable 1 Regular channel analog watchdog enable 22 IWDEN Inserted channel analog watchdog enable 0 Inserted channel analog watchdog disable 1 Inserted channel analog watchdog enable 21 20 Reserved Must be ke...

Page 176: ...nnels enable 10 ICA Inserted channel group convert automatically 0 Inserted channel group convert automatically disable 1 Inserted channel group convert automatically enable 9 WDSC When in scan mode analog watchdog is effective on a single channel 0 Analog watchdog is effective on all channels 1 Analog watchdog is effective on a single channel 8 SM Scan mode 0 scan mode disable 1 scan mode enable ...

Page 177: ...1 20 19 18 17 16 Reserved TSVREN SWRCST SWICST ETERC ETSRC 2 0 Reserved rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETEIC ETSIC 2 0 DAL Reserved DMA Reserved RSTCLB CLB CTN ADCON rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 TSVREN Channel 16 and 17 enable of ADC0 0 Channel 16 and 17 of ADC0 disable 1 Channel 16 and 17 of ADC0 enable 22 SWR...

Page 178: ...able for inserted channel 0 External trigger for inserted channel disable 1 External trigger for inserted channel enable 14 12 ETSIC 2 0 External trigger select for inserted channel For ADC0 and ADC1 000 Timer 0 TRGO 001 Timer 0 CH3 010 Timer 1 TRGO 011 Timer 1 CH0 100 Timer 2 CH3 101 Timer 3 TRGO 110 EXTI line15 111 SWICST 11 DAL Data alignment 0 LSB alignment 1 MSB alignment 10 9 Reserved Must b...

Page 179: ...Sample time register 0 ADC_SAMPT0 Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SPT17 2 0 SPT16 2 0 SPT15 2 1 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPT15 0 SPT14 2 0 SPT13 2 0 SPT12 2 0 SPT11 2 0 SPT10 2 0 rw rw rw rw rw rw Bits Fields Descriptions 31 24 Reserved Must be kept at reset va...

Page 180: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 SPT5 0 SPT4 2 0 SPT3 2 0 SPT2 2 0 SPT1 2 0 SPT0 2 0 rw rw rw rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 27 SPT9 2 0 refer to SPT0 2 0 description 26 24 SPT8 2 0 refer to SPT0 2 0 description 23 21 SPT7 2 0 refer to SPT0 2 0 description 20 18 SPT6 2 0 refer to SPT0 2 0 description 17 15 SPT5 2 0 refer to SPT0 2 0 description 14 12 S...

Page 181: ...Reserved Must be kept at reset value 11 0 IOFF 11 0 Data offset for inserted channel x These bits will be subtracted from the raw converted data when converting inserted channels The conversion result can be read from in the ADC_IDATAx registers 11 8 7 Watchdog high threshold register ADC_WDHT Address offset 0x24 Reset value 0x0000 0FFF This register has to be accessed by word 32 bit 31 30 29 28 2...

Page 182: ...ow threshold These bits define the low threshold for the analog watchdog 11 8 9 Regular sequence register 0 ADC_RSQ0 Address offset 0x2C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RL 3 0 RSQ15 4 1 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSQ15 0 RSQ14 4 0 RSQ13 4 0 RSQ12 4 0 rw rw rw rw Bits Fields Description...

Page 183: ...ons 31 30 Reserved Must be kept at reset value 29 25 RSQ11 4 0 refer to RSQ0 4 0 description 24 20 RSQ10 4 0 refer to RSQ0 4 0 description 19 15 RSQ9 4 0 refer to RSQ0 4 0 description 14 10 RSQ8 4 0 refer to RSQ0 4 0 description 9 5 RSQ7 4 0 refer to RSQ0 4 0 description 4 0 RSQ6 4 0 refer to RSQ0 4 0 description 11 8 11 Regular sequence register 2 ADC_RSQ2 Address offset 0x34 Reset value 0x0000 0...

Page 184: ...22 21 20 19 18 17 16 Reserved IL 1 0 ISQ3 4 1 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISQ3 0 ISQ2 4 0 ISQ1 4 0 ISQ0 4 0 rw rw rw rw Bits Fields Descriptions 31 22 Reserved Must be kept at reset value 21 20 IL 1 0 Inserted channel group length The total number of conversion in Inserted group equals to IL 1 0 1 19 15 ISQ3 4 0 refer to ISQ0 4 0 description 14 10 ISQ2 4 0 refer to ISQ0 4 0 descrip...

Page 185: ...on data These bits contain the number n conversion result which is read only 11 8 14 Regular data register ADC_RDATA Address offset 0x4C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADC1RDTR 15 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDATA 15 0 r Bits Fields Descriptions 31 16 ADC1RDTR 15 0 ADC1 regular channel data In AD...

Page 186: ...TOVS Triggered Oversampling This bit is set and cleared by software 0 All oversampled conversions for a channel are done consecutively after a trigger 1 Each conversion needs a trigger for a oversampled channel and the number of triggers is determined by the oversampling ratio OVSR 2 0 Note Software is allowed to write this bit only when ADCON 0 which ensures that no conversion is ongoing 8 5 OVSS...

Page 187: ...64x 110 128x 111 256x Note Software is allowed to write this bit only when ADCON 0 which ensures that no conversion is ongoing 1 Reserved Must be kept at reset value 0 OVSEN Oversampler Enable This bit is set and cleared by software 0 Oversampler disabled 1 Oversampler enabled Note Software is allowed to write this bit only when ADCON 0 which ensures that no conversion is ongoing ...

Page 188: ... can be optionally buffered for higher drive capability The two DACs can work independently or concurrently 12 2 Characteristics DAC s main features are as follows 12 bit resolution Left or right data alignment DMA capability for each channel Conversion update synchronously Conversion triggered by external triggers Configurable internal buffer Input voltage reference VREF Noise wave generation LFS...

Page 189: ...1 DAC pins Name Description Signal type VDDA Analog power supply Input analog supply VSSA Ground for analog power supply Input analog supply ground VREF Positive reference voltage for the DAC 2 4 V VREF VDDA Input analog positive reference DAC_OUTx DACx analog output Analog output signal The GPIO pins PA4 for DAC0 PA5 for DAC1 should be configured to analog mode before enable the DAC module 12 3 F...

Page 190: ... DAC external triggers are selected by the DTSELx bits in the DAC_CTL register Table 12 2 External triggers of DAC DTSELx 2 0 Trigger Source Trigger Type 000 TIMER5_TRGO Internal on chip signal 001 TIMER2_TRGO 010 TIMER6_TRGO 011 TIMER4_TRGO 100 TIMER1_TRGO 101 TIMER3_TRGO 110 EXTI9 External signal 111 SWTRIG Software trigger The TIMERx_TRGO signals are generated from the timers while the software...

Page 191: ...LFSR in the DAC control logic it controls the LFSR noise signal which is added to the DACx_DH value When the configured DAC noise wave bit width is less than 12 the noise signal equals to the LSB DWBWx bits of the LFSR register while the MSB bits are masked Figure 12 2 DAC LFSR algorithm 9 7 8 6 5 4 3 2 1 11 10 0 X6 X0 X4 X XOR X12 NOR 12 Triangle noise mode in this mode a triangle signal is added...

Page 192: ... the two DACs work at the same time for maximum bus bandwidth utilization in specific applications two DACs can be configured in concurrent mode In concurrent mode two DACs data transfer DACx_DH to DACx_DO will be at the same time There are three concurrent registers that can be used to load the DACx_DH value DACC_R8DH DACC_R12DH and DACC_L12DH You just need to access a unique register to realize ...

Page 193: ...th of the noise wave signal of DAC1 These bits indicate that unmask LFSR bit n 1 0 in LFSR noise mode or the amplitude of the triangle is 2 n 1 1 in triangle noise mode where n is the bit width of wave 0000 The bit width of the wave signal is 1 0001 The bit width of the wave signal is 2 0010 The bit width of the wave signal is 3 0011 The bit width of the wave signal is 4 0100 The bit width of the ...

Page 194: ...abled 1 DAC1 enabled 15 13 Reserved Must be kept at reset value 12 DDMAEN0 DAC0 DMA enable 0 DAC0 DMA mode disabled 1 DAC0 DMA mode enabled 11 8 DWBW0 3 0 DAC0 noise wave bit width These bits specify bit width of the noise wave signal of DAC0 These bits indicate that unmask LFSR bit n 1 0 in LFSR noise mode or the amplitude of the triangle is 2 n 1 1 in triangle noise mode where n is the bit width...

Page 195: ...0 Timer 5 TRGO 001 Timer 2 TRGO 010 Timer 6 TRGO 011 Timer 4 TRGO 100 Timer 1 TRGO 101 Timer 3 TRGO 110 EXTI line 9 111 Software trigger 2 DTEN0 DAC0 trigger enable 0 DAC0 trigger disabled 1 DAC0 trigger enabled 1 DBOFF0 DAC0 output buffer turn off 0 DAC0 output buffer turns on to reduce the output impedance and improve the driving capability 1 DAC0 output buffer turn off 0 DEN0 DAC0 enable 0 DAC0...

Page 196: ...his register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DAC0_DH 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 DAC0_DH 11 0 DAC0 12 bit right aligned data These bits specify the data that is to be converted by DAC0 12 4 4 DAC0 12 bit left aligned data holding register DA...

Page 197: ...rved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DAC0_DH 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 DAC0_DH 7 0 DAC0 8 bit right aligned data These bits specify the MSB 8 bits of the data that is to be converted by DAC0 12 4 6 DAC1 12 bit right aligned data holding register DAC1_R12DH Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed...

Page 198: ...set value 15 4 DAC1_DH 11 0 DAC1 12 bit left aligned data These bits specify the data that is to be converted by DAC1 3 0 Reserved Must be kept at reset value 12 4 8 DAC1 8 bit right aligned data holding register DAC1_R8DH Address offset 0x1C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 ...

Page 199: ...These bits specify the data that is to be converted by DAC1 15 12 Reserved Must be kept at reset value 11 0 DAC0_DH 11 0 DAC0 12 bit right aligned data These bits specify the data that is to be converted by DAC0 12 4 10 DAC concurrent mode 12 bit left aligned data holding register DACC_L12DH Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 ...

Page 200: ...served 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAC1_DH 7 0 DAC0_DH 7 0 rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 8 DAC1_DH 7 0 DAC1 8 bit right aligned data These bits specify the MSB 8 bit of the data that is to be converted by DAC1 7 0 DAC0_DH 7 0 DAC0 8 bit right aligned data These bits specify the MSB 8 bit of the data that is to be converted by DAC0 12 4 12 DA...

Page 201: ... data output register DAC1_DO Address offset 0x30 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DAC1_DO 11 0 r Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 DAC1_DO 11 0 DAC1 data output These bits which are read only reflect the data that is ...

Page 202: ...free clock source IRC40K Thereupon the FWDGT can operate even if the main clock fails It s suitable for the situation that requires an independent environment and lower timing accuracy The free watchdog timer causes a reset when the internal down counter reaches 0 The register write protection function in free watchdog can be enabled to prevent it from changing the configuration unexpectedly 13 1 ...

Page 203: ...void reset the software should reload the counter before the counter reaches 0x000 The FWDGT_PSC register and the FWDGT_RLD register are write protected Before writing these registers the software should write the value 0x5555 to the FWDGT_CTL register These registers will be protected again by writing any other value to the FWDGT_CTL register When an update operation of the prescaler register FWD...

Page 204: ...dby mode immediately more than 3 IRC40K clock interval must be inserted in the middle of reload and deepsleep standby mode commands by software setting For all the GD32VF103 devices when software finished the executing operation of FWDGT if the MCU needs enter the deepsleep standby mode immediately it is at least 100 us interval left between the two instructions For all the GD32VF103 devices if yo...

Page 205: ... values 0x5555 Disable the FWDGT_PSC and FWDGT_RLD write protection 0xCCCC Start the free watchdog counter When the counter reduces to 0 the free watchdog generates a reset 0xAAAA Reload the counter Prescaler register FWDGT_PSC Address offset 0x04 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved...

Page 206: ...erved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RLD 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 RLD 11 0 Free watchdog timer counter reload value Write 0xAAAA in the FWDGT_CTL register will reload the FWDGT counter with the RLD value These bits are write protected Write 0x5555 in the FWDGT_CTL register before writing these bits During a write operation to ...

Page 207: ...Free watchdog timer counter reload value update During a write operation to FWDGT_RLD register this bit is set and the value read from FWDGT_RLD register is invalid This bit is reset by hardware after the update operation of FWDGT_RLD register 0 PUD Free watchdog timer prescaler value update During a write operation to FWDGT_PSC register this bit is set and the value read from FWDGT_PSC register i...

Page 208: ... watchdog timer clock is prescaled from the APB1 clock The window watchdog timer is suitable for the situation that requires an accurate timing 13 2 2 Characteristics Programmable free running 7 bit downcounter Generate reset in two conditions when WWDGT is enabled Reset when the counter reached 0x3F The counter is refreshed when the value of the counter is greater than the window register value E...

Page 209: ...ister WWDGT_CFG specifies the window value The software can prevent the reset event by reloading the downcounter when counter value is less than the window value and greater than 0x3F otherwise the watchdog causes a reset The early wakeup interrupt EWI is enabled by setting the EWIE bit in the WWDGT_CFG register and the interrupt is generated when the counter reaches 0x40 or the counter is refresh...

Page 210: ...B1 clock period measured in ms Refer to the table below for the minimum and maximum values of the tWWDGT Table 13 2 Min max timeout value at 54 MHz fPCLK1 Prescaler divider PSC 1 0 Min timeout value CNT 6 0 0x40 Max timeout value CNT 6 0 0x7F 1 1 00 75 8 μs 4 85ms 1 2 01 151 7 μs 9 7 ms 1 4 10 303 4 μs 19 4 ms 1 8 11 606 8 μs 38 8 ms If the WWDGT_HOLD bit in DBG module is cleared the WWDGT continu...

Page 211: ...ardware reset Writing 0 has no effect 0 Window watchdog timer disabled 1 Window watchdog timer enabled 6 0 CNT 6 0 The value of the watchdog timer counter A reset occurs when the value of this counter decreases from 0x40 to 0x3F When the value of this counter is greater than the window value writing this counter also causes a reset Configuration register WWDGT_CFG Address offset 0x04 Reset value 0...

Page 212: ...CNT bits in WWDGT_CTL is written when the value of the watchdog counter is greater than the Window value Status register WWDGT_STAT Address offset 0x08 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EWIF rw Bits Fields Descriptions 31 1 Reserved Must be ...

Page 213: ...clock domain this clock must be at least 4 times slower than the PCLK1 clock RTC clock source A HXTAL clock divided by 128 B LXTAL oscillator clock C IRC40K oscillator clock Maskable interrupt source A Alarm interrupt B Second interrupt C Overflow interrupt 14 3 Function overview The RTC circuits consist of two major units APB interface located in PCLK1 clock domain and RTC core located in RTC clo...

Page 214: ... BKPIEN bits in the RCU_APB1EN register to enable the power and backup interface clocks 2 Enable access to the backup registers and RTC by setting the BKPWEN bit in the PMU_CTL 14 3 2 RTC reading The APB interface and RTC core are located in two different power supply domains In the RTC core only counter and divider registers are readable registers And the values in the two registers and the RTC f...

Page 215: ... registers d Exit Configuration mode by clearing the CMF bit in the RTC_CTL register e Wait until the value of LWOFF bit in the RTC_CTL register sets to 1 14 3 4 RTC flag assertion Before the update of the RTC Counter the RTC second interrupt flag SCIF is asserted on the last RTCCLK cycle Before the counter equal to the RTC Alarm value which stored in the Alarm register increases by one the RTC Al...

Page 216: ...lag can be cleared by software RTCCLK 2 3 1 0 3 1 1 3 3 2 1 0 2 0 2 0 2 1 Figure 14 3 RTC second and overflow waveform example RTC_PSC 3 RTC_ Overflow FFFFFFFD FFFFFFFE FFFFFFFF 0 1 RTC_Second RTC_ CNT OVIF RTC_PSC OVIF flag can be cleared by software RTCCLK 2 3 1 0 3 1 1 3 3 2 1 0 2 0 2 0 2 1 ...

Page 217: ...erved Must be kept at reset value 2 OVIE Overflow interrupt enable 0 Disable overflow interrupt 1 Enable overflow interrupt 1 ALRMIE Alarm interrupt enable 0 Disable alarm interrupt 1 Enable alarm interrupt 0 SCIE Second interrupt enable 0 Disable second interrupt 1 Enable second interrupt 14 4 2 RTC control register RTC_CTL Address offset 0x04 Reset value 0x0020 This register can be accessed by h...

Page 218: ... in RTC_INTEN 1 ALRMIF Alarm interrupt flag 0 Alarm event not detected 1 Alarm event detected An interrupt named RTC global interrupt will occur if the ALRMIE bit is set in RTC_INTEN And another interrupt named the RTC Alarm interrupt will occur if the EXTI 17 is enabled in interrupt mode 0 SCIF Second interrupt flag 0 Second event not detected 1 Second event detected An interrupt will occur if th...

Page 219: ...pt at reset value 15 0 PSC 15 0 RTC prescaler value low The frequency of SC_CLK is the RTCCLK frequency divided by PSC 19 0 1 14 4 5 RTC divider high register RTC_DIVH Address offset 0x10 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DIV 19 16 r Bits Fields ...

Page 220: ...C_CNTH Address offset 0x18 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 31 16 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CNT 31 16 RTC counter value high 14 4 8 RTC counter low register RTC_CNTL Address offset 0x1C Reset value 0x...

Page 221: ...16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALRM 31 16 w Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 ALRM 31 16 RTC alarm value high 14 4 10 RTC alarm low register RTC_ALRML Address offset 0x24 Reset value 0xFFFF This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 222: ...ction 1 2 TRGO TO DAC DMA 3 Debug Mode 1 TIMER0 ITI0 TIMER4_TRGO ITI1 TIMER1_TRGO ITI2 TIMER2_TRGO ITI3 TIMER3_TRGO 2 TIMER1 ITI0 TIMER0_TRGO ITI1 refer to note 4 ITI2 TIMER2_TRGO ITI3 TIMER3_TRGO TIMER2 ITI0 TIMER0_TRGO ITI1 TIMER1_TRGO ITI2 TIMER4_TRGO ITI3 TIMER3_TRGO TIMER3 ITI0 TIMER0_TRGO ITI1 TIMER1_TRGO ITI2 TIMER2_TRGO ITI3 0 TIMER4 ITI0 TIMER1_TRGO ITI1 TIMER2_TRGO ITI2 TIMER3_TRGO ITI3 ...

Page 223: ...Total channel num 4 Counter width 16 bit Clock source of timer is selectable internal clock internal trigger external input external trigger Multiple counter modes up counting down counting and center aligned counting Quadrature decoder used for motion tracking and determination of both rotation direction and position Hall sensor function used for 3 phase motor control Programmable prescaler 16 bi...

Page 224: ...oller TIMERx_TRGO DMA REQ ACK TIMERx_CH0 TIMERx_CH1 TIMERx_CH2 TIMERx_CH3 TIMERx_TG TIMERx_UP TIMERx_CMT Interrupt break update trig ctrl cap cmt CH1_O CH1_ON CH2_O CH2_ON CH3_O req en direct req set PSC PSC_CLK TIMER_CK ETIFP 15 1 4 Function overview Clock selection The clock source of the advanced timer can be either the CK_TIMER or an alternate clock source controlled by SMC bits TIMERx_SMCFG b...

Page 225: ...be selected by setting SMC 2 0 to 0x7 and the TRGS 2 0 to 0x0 0x1 0x2 or 0x3 SMC1 1 b1 external clock mode 1 External input ETI is selected as timer clock source The TIMER_CK which drives counter s prescaler to count can be triggered by the event of rising or falling edge on the external pin ETI This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1 The other way to se...

Page 226: ... Otherwise the update event is generated each time when counter overflows The counting direction bit DIR in the TIMERx_CTL0 register should be set to 0 for the up counting mode Whenever if the update event software trigger is enabled by setting the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and an update event will be generated If the UPDIS bit in TIMERx_CTL0 r...

Page 227: ...0 1 CEN CNT_CLK PSC_CLK CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 05 06 07 Update event UPE Update interrupt flag UPIF CNT_REG 5F 60 Update event UPE Update interrupt flag UPIF Hardware set Software clear Hardware set PSC 0 PSC 1 TIMER_CK 08 63 62 61 00 01 02 03 CNT_CLK PSC_CLK ...

Page 228: ...t again from the counter reload value If the repetition counter is set the update event will be generated after TIMERx_CREP 1 times of underflow Otherwise the update event is generated each time when counter underflows The counting direction bit DIR in the TIMERx_CTL0 register should be set to 1 for the down counting mode When the update event is set by the UPG bit in the TIMERx_SWEVG register the...

Page 229: ...NT_CLK PSC_CLK CNT_REG 05 04 03 02 01 00 63 62 61 60 5F 5E 5C 5B Update event UPE Update interrupt flag UPIF CNT_REG 04 03 Update event UPE Update interrupt flag UPIF Hardware set Software clear Hardware set TIMERx_PSC PSC 0 TIMERx_PSC PSC 1 TIMER_CK 5A 00 01 02 63 62 61 CNT_CLK PSC_CLK ...

Page 230: ...w event when the counter counts to TIMERx_CREP 1 in the count up direction and generates an underflow event when the counter counts to 1 in the count down direction The counting direction bit DIR in the TIMERx_CTL0 register is read only and indicates the counting direction when in the center aligned counting mode The counting direction is updated by hardware automatically Setting the UPG bit in th...

Page 231: ...IMER_CK 01 02 62 63 62 61 UPIF CHxIF CHxIF TIMERx_CTL0 CAM 2 b10 upcount only TIMERx_CTL0 CAM 2 b10 downcount only CHxIF Repetition counter Repetition counter is used to generate the update event or update the timer registers only after a given number N 1 cycles of the counter where N is the value of CREP bit in TIMERx_CREP register The repetition counter is decremented at each counter overflow in...

Page 232: ...CREP was written after starting the counter Figure 15 9 Repetition counter timing chart of center aligned counting mode CEN 03 02 01 00 01 02 62 63 62 61 01 00 Underflow Overflow TIMERx_CREP 0x0 TIMER_CK 01 02 62 63 62 61 UPIF TIMERx_CREP 0x1 01 00 01 02 62 63 62 61 UPIF UPIF TIMERx_CREP 0x2 CNT_CLK Figure 15 10 Repetition counter timing chart of up counting mode CEN CNT_REG 60 61 62 63 00 01 62 6...

Page 233: ...ach channel is built around a channel capture compare register including an input stage a channel controller and an output stage Input capture mode Input capture mode allows the channel to perform measurements such as pulse timing frequency period duty cycle and so on The input stage consists of a digital filter a channel polarity selection edge detection and a channel prescaler When a selected ed...

Page 234: ...er makes several input events generate one effective capture event On the capture event TIMERx_CHxCV will store the value of counter So the process can be divided to several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal and quality of requested signal configure compatible CHxCAPFLT Step2 Edge selection CHxP CHxNP in TIMERx_CHCTL2 Rising edge or fall...

Page 235: ...complementary protection register Dead Time Output enable and polarity selector CHxP CHxNP CHxE CHxNE OxCPRE CHx_O CHx_ON Figure 15 14 Output compare logic CH3_O Capture compare register CH3CV Counter output comparator Compare output control CH3COMCTL Output enable and polarity selector CH3P CH3E O3CPRE CH3_O CNT CH3CV CNT CH3CV CNT CH3CV Figure 15 13 Output compare logic with complementary output...

Page 236: ...annel the channel n output can be set cleared or toggled based on CHxCOMCTL When the counter reaches the value in the TIMERx_CHxCV register the CHxIF bit will be set and the channel n interrupt is generated if CHxIE 1 And the DMA request will be asserted if CxCDE 1 So the process can be divided into several steps as below Step1 Clock Configuration Such as clock source clock prescaler and so on Ste...

Page 237: ...Edge aligned PWM and CAPWM Center aligned PWM The EAPWM s period is determined by TIMERx_CAR and the duty cycle is determined by TIMERx_CHxCV Figure 15 16 Timing chart of EAPWM shows the EAPWM output and interrupts waveform The CAPWM s period is determined by 2 TIMERx_CAR the duty cycle is determined by 2 TIMERx_CHxCV Figure 15 17 Timing chart of CAPWM shows the CAPWM output and interrupts wavefor...

Page 238: ... 2 b01 down only CAM 2 b10 up only CHxIF CHxOF CAM 2 b11 up down CHxIF CHxOF Channel output prepare signal As is shown in Figure 15 13 Output compare logic with complementary output x 0 1 2 when TIMERx is configured in compare match output mode a middle signal which is OxCPRE signal Channel x output prepare signal will be generated before the channel outputs signal The OxCPRE signal type is define...

Page 239: ...chieved by configuring the CHxCOMCTL field to 0x04 0x05 The output can be forced to an inactive active level irrespective of the comparison condition between the values of the counter and the TIMERx_CHxCV Configure the CHxCOMCEN bit to 1 in the TIMERx_CHCTL0 register the OxCPRE signal can be forced to 0 when the ETIFP signal derived from the external ETI pin is set to a high level The OxCPRE signa...

Page 240: ... clock is enable CHx_O ISOx CHx_ON ISOxN 1 0 1 1 0 0 1 0 0 CHx_O CHx_ON LOW CHx_O CHx_ON output disable 1 CHx_O LOW CHx_O output disable CHx_ON OxCPRE CHxNP CHx_ON output enable 1 0 CHx_O OxCPRE CHxP CHx_O output enable CHx_ON LOW CHx_ON output disable 1 CHx_O OxCPRE CHxP CHx_O output enable CHx_ON OxCPRE CHxNP CHx_ON output enable 1 0 0 CHx_O CHxP CHx_O output disable CHx_ON CHxNP CHx_ON output d...

Page 241: ...nt TIMERx counter CHxVAL occurs again OxCPRE is cleared and CHx_O signal will be cleared at once while CHx_ON signal remains at the low level until the end of the dead time delay Sometimes we can see corner cases about the dead time insertion For example the dead time delay is greater than or equal to the duty cycle of the CHx_O signal then the CHx_O signal is always inactive as show in the Figure...

Page 242: ...e to a break the break high active OxCPRE CHx_O CHx_ON BRKIN CHx_O CHx_ON CHx_O CHx_ON ISOx ISOxN ISOx ISOxN CHxEN 1 CHxNEN 1 CHxP 0 CHxNP 0 ISOx ISOxN CHxEN 1 CHxNEN 0 CHxP 0 CHxNP 0 ISOx ISOxN CHxEN 1 CHxNEN 0 CHxP 0 CHxNP 0 ISOx ISOxN Quadrature decoder The quadrature decoder function uses two quadrature inputs CI0 and CI1 derived from the TIMERx_CH0 and TIMERx_CH1 pins respectively to interact...

Page 243: ...E1 Low Up Down CI1 only counting CI0FE0 High Up Down CI0FE0 Low Down Up CI0 and CI1 counting CI1FE1 High Down Up X X CI1FE1 Low Up Down X X CI0FE0 High X X Up Down CI0FE0 Low X X Down Up Note means no counting X means impossible Figure 15 20 Example of counter operation in encoder interface mode CI0 CI1 UP down Counter Figure 15 21 Example of encoder interface mode with CI0FE0 polarity inverted CI...

Page 244: ...our request About the TIMER_in it need have input XOR function so you can choose from Advanced GeneralL0 TIMER And TIMER_out need have functions of complementary and Dead time so only advanced timer can be chosen Else based on the timers internal connection relationship pair s timers can be selected TIMER_in TIMER2 TIMER_out TIMER0 ITI2 And so on After getting appropriate timers combination and wi...

Page 245: ...y the SMC 2 0 bits in the TIMERx_SMCFG register The input trigger of these modes can be selected by the TRGS 2 0 bits in the TIMERx_SMCFG register Table 15 4 Slave mode example table Mode Selection Source Selection Polarity Selection Filter and Prescaler LIST SMC 2 0 3 b100 restart mode 3 b101 pause mode 3 b110 event mode TRGS 2 0 000 ITI0 001 ITI1 010 ITI2 011 ITI3 100 CI0F_ED 101 CI0FE0 If CI0FE...

Page 246: ... 2 0 3 b000 ITI0 is selected For ITI0 no polarity selector can be used For the ITI0 no filter and prescaler can be used Figure 15 24 Restart mode TIMER_CK CEN CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 00 01 02 UPIF ITI0 TRGIF Internal sync delay Exam2 Pause mode The counter will be paused when the trigger input is low and it will start when the trigger input is high TRGS 2 0 3 b101 CI0FE0 is select...

Page 247: ...n generate a pulse and then keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software If the CEN bit is cleared to 0 by software the counter will be stopped and its value will be held If the CEN bit is automatically cleared to 0 by a hardware update event the counter will be reinitialized In the single pulse mode the active edge of trigger which sets...

Page 248: ...res present several examples of trigger selection for the master and slave modes Figure 15 28 TIMER0 Master Slave mode timer example shows the timer0 trigger selection when it is configured in slave mode Figure 15 28 TIMER0 Master Slave mode timer example TIMER0 TIMER 4 Prescaler Counter Master mode control Trigger selection ITI0 IT1 ITI1 CI0F_ED CI0FE0 CI1FE1 ETIFP TRGS Slave mode control Prescal...

Page 249: ...current value on the divided internal clock after trigger by TIMER2 enable output When Timer0 receives the trigger signal its CEN bit is automatically set and the counter counts until we disable TIMER0 Both counter clock frequencies are divided by 3 by the prescaler compared to TIMER_CK fCNT_CLK fTIMER_CK 3 Do as follow 1 Configure TIMER2 master mode to send its enable signal as trigger output MMC...

Page 250: ...MER0 with the enable output of TIMER2 Refer to Figure 15 31 Pause TIMER0 with enable signal of TIMER2 TIMER0 counts on the divided internal clock only when TIMER2 is enable Both counter clock frequencies are divided by 3 by the prescaler compared to TIMER_CK fCNT_CLK fTIMER_CK 3 Do as follow 1 Configure TIMER2 input master mode and output enable signal as trigger output MMC 3 b001 in the TIMER2_CT...

Page 251: ...n pause mode SMC 3 b101 in TIMER0_SMCFG register 5 Enable TIMER0 by writing 1 in the CEN bit TIMER0_CTL0 register 6 Start TIMER2 by writing 1 in the CEN bit TIMER2_CTL0 register Figure 15 32 Pause TIMER0 with O0CPREF signal of Timer2 TIMER_CK TIMER2_CNT_REG TIMER0_CNT_REG TIMER2_CEN 61 62 63 11 12 13 TIMER0_TRGIF Using an external trigger to start 2 timers synchronously We configure the start of T...

Page 252: ...ters are TIMERx_DMACFG and TIMERx_DMATB Corresponding DMA request bit should be asserted to enable DMA request for internal interrupt event TIMERx will send a request to DMA when the interrupt event occurs DMA is configured to M2P memory to peripheral mode and the address of TIMERx_DMATB is configured to PADDR peripheral base address then DMA will access the TIMERx_DMATB In fact TIMERx_DMATB regis...

Page 253: ...will be sent by TIMERx If one more DMA request event occurs TIMERx will repeat the process above Timer debug mode When the RISC V core halted and the TIMERx_HOLD configuration bit in DBG_CTL register is set to 1 the TIMERx counter stops ...

Page 254: ...R register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns mode selection 00 No center aligned mode edge aligned mode The direction of the counter is specified by the DIR bit 01 Center aligned and counting down assert mode The counter counts under center aligned and channel is configured in output mode CHxMS 00 in TIMERx_CHCTL0 register Only when the...

Page 255: ...he update event generation 0 update event enable The update event is generate and the buffered registers are loaded with their preloaded values when one of the following events occurs The UPG bit is set The counter generates an overflow or underflow event The slave mode controller generates an update event 1 update event disable The buffered registers keep their value while the counter and the pre...

Page 256: ...ied only when PROT 1 0 bits in TIMERx_CCHP register is 00 7 TI0S Channel 0 trigger input selection 0 The TIMERx_CH0 pin input is selected as channel 0 trigger input 1 The result of combinational XOR of TIMERx_CH0 CH1 and CH2 pins is selected as channel 0 trigger input 6 4 MMC 2 0 Master mode control These bits control the selection of TRGO signal which is sent in master mode to slave timers for sy...

Page 257: ...ter update control When the commutation control shadow enable for CHxEN CHxNEN and CHxCOMCTL bits are set CCSE 1 these shadow registers update are controlled as below 0 The shadow registers update by when CMTG bit is set 1 The shadow registers update by when CMTG bit is set or a rising edge of TRGI occurs When a channel does not have a complementary output this bit has no effect 1 Reserved Must be...

Page 258: ...rigger prescaler The frequency of external trigger signal ETIFP must not be at higher than 1 4 of TIMER_CK frequency When the external trigger signal is a fast clock the prescaler can be enabled to reduce ETIFP frequency 00 Prescaler disable 01 ETIFP frequency will be divided by 2 10 ETIFP frequency will be divided by 4 11 ETIFP frequency will be divided by 8 11 8 ETFC 3 0 External trigger filter ...

Page 259: ... Slave mode control 000 Disable mode The slave mode is disabled The prescaler is clocked directly by the internal clock TIMER_CK when CEN bit is set high 001 Quadrature decoder mode 0 The counter counts on CI1FE1 edge while the direction depends on CI0FE0 level 010 Quadrature decoder mode 1 The counter counts on CI0FE0 edge while the direction depends on CI1FE1 level 011 Quadrature decoder mode 2 ...

Page 260: ...ation DMA request enable 0 disabled 1 enabled 12 CH3DEN Channel 3 capture compare DMA request enable 0 disabled 1 enabled 11 CH2DEN Channel 2 capture compare DMA request enable 0 disabled 1 enabled 10 CH1DEN Channel 1 capture compare DMA request enable 0 disabled 1 enabled 9 CH0DEN Channel 0 capture compare DMA request enable 0 disabled 1 enabled 8 UPDEN Update DMA request enable 0 disabled 1 enab...

Page 261: ...served CH3OF CH2OF CH1OF CH0OF Reserved BRKIF TRGIF CMTIF CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 15 13 Reserved Must be kept at reset value 12 CH3OF Channel 3 over capture flag Refer to CH0OF description 11 CH2OF Channel 2 over capture flag Refer to CH0OF description 10 CH1OF Channel 1 over capture flag Refer to...

Page 262: ...are when channel s commutation event occurs and cleared by software 0 No channel commutation interrupt occurred 1 Channel commutation interrupt occurred 4 CH3IF Channel 3 s capture compare interrupt flag Refer to CH0IF description 3 CH2IF Channel 2 s capture compare interrupt flag Refer to CH0IF description 2 CH1IF Channel 1 s capture compare interrupt flag Refer to CH0IF description 1 CH0IF Chann...

Page 263: ...ion This bit is set by software and cleared by hardware automatically When this bit is set channel s capture compare control registers CHxEN CHxNEN and CHxCOMCTL bits are updated based on the value of CCSE in the TIMERx_CTL1 0 No affect 1 Generate channel s c c control update event 4 CH3G Channel 3 s capture or compare event generation Refer to CH0G description 3 CH2G Channel 2 s capture or compar...

Page 264: ...H0CAPPSC 1 0 rw rw rw rw rw rw Output compare mode Bits Fields Descriptions 15 CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14 12 CH1COMCTL 2 0 Channel 1 compare output control Refer to CH0COMCTL description 11 CH1COMSEN Channel 1 output compare shadow enable Refer to CH0COMSEN description 10 CH1COMFEN Channel 1 output compare fast enable Refer to CH0COMSEN descri...

Page 265: ...ler than TIMERx_CH0CV else inactive When counting down O0CPRE is inactive as long as the counter is larger than TIMERx_CH0CV else active 111 PWM mode1 When counting up O0CPRE is inactive as long as the counter is smaller than TIMERx_CH0CV else active When counting down O0CPRE is active as long as the counter is larger than TIMERx_CH0CV else inactive When configured in PWM mode the O0CPRE level cha...

Page 266: ...s input IS0 is connected to CI1FE0 11 Channel 0 is configured as input IS0 is connected to ITS This mode is working only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register Input capture mode Bits Fields Descriptions 15 12 CH1CAPFLT 3 0 Channel 1 input capture filter control Refer to CH0CAPFLT description 11 10 CH1CAPPSC 1 0 Channel 1 input capture prescaler Refer t...

Page 267: ...s register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3COM CEN CH3COMCTL 2 0 CH3COM SEN CH3COM FEN CH3MS 1 0 CH2COM CEN CH2COMCTL 2 0 CH2COM SEN CH2COM FEN CH2MS 1 0 CH3CAPFLT 3 0 CH3CAPPSC 1 0 CH2CAPFLT 3 0 CH2CAPPSC 1 0 rw rw rw rw rw rw Output compare mode Bits Fields Descriptions 15 CH3COMCEN Channel 3 output compare clear enable Refer to CH0COMC...

Page 268: ...ERx_CH2CV 010 Clear the channel output O2CPRE signal is forced low when the counter matches the output compare register TIMERx_CH2CV 011 Toggle on match O2CPRE toggles when the counter matches the output compare register TIMERx_CH2CV 100 Force low O2CPRE is forced low level 101 Force high O2CPRE is forced high level 110 PWM mode0 When counting up O2CPRE is active as long as the counter is smaller ...

Page 269: ...ies the work mode of the channel and the input signal selection This bit field is writable only when the channel is not active CH2EN bit in TIMERx_CHCTL2 register is reset 00 Channel 2 is configured as output 01 Channel 2 is configured as input IS2 is connected to CI2FE2 10 Channel 2 is configured as input IS2 is connected to CI3FE2 11 Channel 2 is configured as input IS2 is connected to ITS This ...

Page 270: ...l input edges 10 Capture is done every 4 channel input edges 11 Capture is done every 8 channel input edges 1 0 CH2MS 1 0 Channel 2 mode selection Same as Output compare mode Channel control register 2 TIMERx_CHCTL2 Address offset 0x20 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH3P CH3EN CH2NP CH2NEN CH2P CH2E...

Page 271: ...when PROT 1 0 bit filed in TIMERx_CCHP register is 11 or 10 and CH0MS 1 0 bit filed in TIMERx_CHCTL0 register is 00 2 CH0NEN Channel 0 complementary output enable When channel 0 is configured in output mode setting this bit enables the complementary output in channel0 0 Channel 0 complementary output disabled 1 Channel 0 complementary output enabled 1 CH0P Channel 0 capture compare function polari...

Page 272: ...0 This bit filed indicates the current counter value Writing to this bit filed can change the value of the counter Prescaler register TIMERx_PSC Address offset 0x28 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw Bits Fields Descriptions 15 0 PSC 15 0 Prescaler value of the counter clock The PSC clock is divided ...

Page 273: ...tions 15 8 Reserved Must be kept at reset value 7 0 CREP 7 0 Counter repetition value This bit filed specifies the update event generation rate Each time the repetition counter counting down to zero an update event is generated The update rate of the shadow registers is also affected by this bit filed when these shadow registers are enabled Channel 0 capture compare value register TIMERx_CH0CV Add...

Page 274: ...ured in output mode this bit filed contains value to be compared to the counter When the corresponding shadow register is enabled the shadow register updates every update event Channel 2 capture compare value register TIMERx_CH2CV Address offset 0x3C Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH2VAL 15 0 rw Bits Fields ...

Page 275: ... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POEN OAEN BRKP BRKEN ROS IOS PROT 1 0 DTCFG 7 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 15 POEN Primary output enable This bit s set by software or automatically by hardware depending on the OAEN bit It is cleared asynchronously by hardware as soon as the break input is active When one of channels is configured in output mode setting this bit enables...

Page 276: ...ut mode 0 When POEN bit is reset the channel output signals CHx_O CHx_ON are disabled 1 When POEN bit is reset he channel output signals CHx_O CHx_ON are enabled with relationship to CHxEN CHxNEN bits in TIMERx_CHCTL2 register This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 10 or 11 9 8 PROT 1 0 Complementary register protect control This bit filed specifies the writ...

Page 277: ...word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DMATC 4 0 Reserved DMATA 4 0 rw rw Bits Fields Descriptions 15 13 Reserved Must be kept at reset value 12 8 DMATC 4 0 DMA transfer count This filed is defined the number of DMA will access R W the register of TIMERx_DMATB 5 b0_0000 1 time transfer 5 b0_0001 2 times transfer 5 b1_0001 18 times transfer 7 5 Reserved Must be kept at reset val...

Page 278: ...6 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMATB 15 0 rw Bits Fields Descriptions 15 0 DMATB 15 0 DMA transfer buffer When a read or write operation is assigned to this register the register located at the address range Start Addr Transfer Timer 4 will be accessed The transfer Timer is calculated by hardware and ranges from 0 to DMATC ...

Page 279: ...is selectable internal clock internal trigger external input external trigger Multiple counter modes up counting down counting and center aligned counting Quadrature decoder used for motion tracking and determination of both rotation direction and position Hall sensor function used for 3 phase motor control Programmable prescaler 16 bit The factor can be changed ongoing Each channel is user config...

Page 280: ...q en direct req set ETIFP 15 2 4 Function overview Clock selection The clock source of the general level0 TIMER can be either the CK_TIMER or an alternate clock source controlled by SMC bits TIMERx_SMCFG bit 2 0 SMC 2 0 3 b000 Internal timer clock CK_TIMER which is from module RCU The default clock source is the CK_TIMER for driving the counter prescaler when the slave mode is disabled SMC 2 0 3 b...

Page 281: ...MC1 1 b1 external clock mode 1 External input ETI is selected as timer clock source The TIMER_CK which drives counter s prescaler to count can be triggered by the event of rising or falling edge on the external pin ETI This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1 The other way to select the ETI signal as the clock source is setting the SMC 2 0 to 0x7 and the ...

Page 282: ...s of overflow Otherwise the update event is generated each time when counter overflows The counting direction bit DIR in the TIMERx_CTL0 register should be set to 0 for the up counting mode Whenever if the update event software trigger is enabled by setting the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and an update event will be generated If the UPDIS bit in ...

Page 283: ...0 1 CEN CNT_CLK PSC_CLK CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 05 06 07 Update event UPE Update interrupt flag UPIF CNT_REG 5F 60 Update event UPE Update interrupt flag UPIF Hardware set Software clear Hardware set PSC 0 PSC 1 TIMER_CK 08 63 62 61 00 01 02 03 CNT_CLK PSC_CLK ...

Page 284: ... restarts to count again from the counter reload value If the repetition counter is set the update event will be generated after TIMERx_CREP 1 times of underflow Otherwise the update event is generated each time when counter underflows The counting direction bit DIR in the TIMERx_CTL0 register should be set to 1 for the down counting mode When the update event is set by the UPG bit in the TIMERx_S...

Page 285: ...CNT_CLK PSC_CLK CNT_REG 05 04 03 02 01 00 63 62 61 60 5F 5E 5C 5B Update event UPE Update interrupt flag UPIF CNT_REG 04 03 Update event UPE Update interrupt flag UPIF Hardware set Software clear Hardware set TIMERx_PSC PSC 0 TIMERx_PSC PSC 1 TIMER_CK 5A 00 01 02 63 62 61 CNT_CLK PSC_CLK ...

Page 286: ...ent when the counter counts to TIMERx_CREP 1 in the count up direction and generates an underflow event when the counter counts to 1 in the count down direction The counting direction bit DIR in the TIMERx_CTL0 register is read only and indicates the counting direction when in the center aligned counting mode The counting direction is updated by hardware automatically Setting the UPG bit in the TI...

Page 287: ... 01 02 62 63 62 61 UPIF CHxIF CHxIF TIMERx_CTL0 CAM 2 b10 upcount only TIMERx_CTL0 CAM 2 b10 downcount only CHxIF Capture compare channels The general level0 Timer has four independent channels which can be used as capture inputs or compare outputs Each channel is built around a channel capture compare register including an input stage a channel controller and an output stage Input capture mode In...

Page 288: ...hen through the edge detector the rising or falling edge is detected by configuring CHxP bit The input capture signal can also be selected from the input signal of other channel or the internal trigger signal by configuring CHxMS bits The IC prescaler makes several input events generate one effective capture event On the capture event TIMERx_CHxCV will store the value of counter So the process can...

Page 289: ...duty cycle Output compare mode In output compare mode the TIMERx can generate timed pulses with programmable position polarity duration and frequency When the counter matches the value in the TIMERx_CHxCV register of an output compare channel the channel n output can be set cleared or toggled based on CHxCOMCTL When the counter reaches the value in the TIMERx_CHxCV register the CHxIF bit will be s...

Page 290: ...unter mode PWM can also be divided into EAPWM Edge aligned PWM and CAPWM Center aligned PWM The EAPWM s period is determined by TIMERx_CAR and the duty cycle is determined by TIMERx_CHxCV Figure 15 44 EAPWM timechart shows the EAPWM output and interrupts waveform The CAPWM period is determined by 2 TIMERx_CAR and duty cycle is determined by 2 TIMERx_CHxCV Figure 15 45 CAPWM timechart shows the CAP...

Page 291: ...AM 2 b11 up down CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode the OxCPRE signal Channel x Output prepare signal is defined by setting the CHxCOMCTL filed The OxCPRE signal has several types of output function These include keeping the original level by setting the CHxCOMCTL field to 0x00 set to 1 by setting the CHxCOMCTL field to 0x01 set to 0 ...

Page 292: ...urs Quadrature decoder The quadrature decoder function uses two quadrature inputs CI0 and CI1 derived from the TIMERx_CH0 and TIMERx_CH1 pins respectively to interact with each other to generate the counter value Setting SMC 0x01 0x02 or 0x03 to select that the counting direction of timer is determined only by the CI0 only by the CI1 or by the CI0 and the CI1 The DIR bit is modified by hardware au...

Page 293: ...y inverted CI0 CI1 UP down Counter Hall sensor function Refer to Advanced timer TIMERx x 0 Slave controller The TIMERx can be synchronized with a trigger in several modes including restart mode pause mode and event mode which is selected by the SMC 2 0 bits in the TIMERx_SMCFG register The input trigger of these modes can be selected by the TRGS 2 0 bits in the TIMERx_SMCFG register ...

Page 294: ...can be used For the CIx configure Filter by CHxCAPFLT no prescaler can be used For the ETIF configure Filter by ETFC and Prescaler by ETPSC Exam1 Restart mode The counter can be clear and restart when a rising trigger input TRGS 2 0 3 b000 ITI0 is the selection For ITI0 no polarity selector can be used For the ITI0 no filter and prescaler can be used Figure 15 48 Restart mode TIMER_CK CEN CNT_REG ...

Page 295: ...ce the timer is set to the single pulse mode it is not necessary to configure the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter Setting the CEN bit to 1 or a trigger signal edge can generate a pulse and then keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software If the CEN bit is cleared to 0 by software the counter w...

Page 296: ...A request for internal interrupt event TIMERx will send a request to DMA when the interrupt event occurs DMA is configured to M2P memory to peripheral mode and the address of TIMERx_DMATB is configured to PADDR peripheral base address then DMA will access the TIMERx_DMATB In fact TIMERx_DMATB register is only a buffer timer will map the TIMERx_DMATB to an internal register appointed by the field o...

Page 297: ...ilters 00 fDTS fTIMER_CK 01 fDTS fTIMER_CK 2 10 fDTS fTIMER_CK 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns mode selection 00 No center aligned mode edge aligned mode The direction of the counter is specified by the DIR bit 01 Center aligned and counting d...

Page 298: ...event The slave mode controller generates an update event 1 When enabled only counter overflow underflow generates an update interrupt or DMA request 1 UPDIS Update disable This bit is used to enable or disable the update event generation 0 update event enable The update event is generate and the buffered registers are loaded with their preloaded values when one of the following events occurs The ...

Page 299: ...n which a slave timer is enabled In this mode the master mode controller selects the counter enable signal TIMERx_EN as TRGO The counter enable signal is set when CEN control bit is set or the trigger input in pause mode is high There is a delay between the trigger input in pause mode and the TRGO output except if the master slave mode is selected 010 Update In this mode the master mode controller...

Page 300: ...ust not be 3 b111 in this case The external clock input will be ETIFP if external clock mode 0 and external clock mode 1 are enabled at the same time Note External clock mode 0 enable is in this register s SMC bit filed 13 12 ETPSC 1 0 External trigger prescaler The frequency of external trigger signal ETIFP must not be at higher than 1 4 of TIMER_CK frequency When the external trigger signal is a...

Page 301: ...ger input 3 ITI3 100 CI0 edge flag CI0F_ED 101 channel 0 input Filtered output CI0FE0 110 channel 1 input Filtered output CI1FE1 111 External trigger input filter output ETIFP These bits must not be changed when slave mode is enabled 3 Reserved Must be kept at reset value 2 0 SMC 2 0 Slave mode control 000 Disable mode The slave mode is disabled The prescaler is clocked directly by the internal cl...

Page 302: ...H2DEN CH1DEN CH0DEN UPDEN Reserved TRGIE Reserved CH3IE CH2IE CH1IE CH0IE UPIE rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 15 Reserved Must be kept at reset value 14 TRGDEN Trigger DMA request enable 0 disabled 1 enabled 13 Reserved Must be kept at reset value 12 CH3DEN Channel 3 capture compare DMA request enable 0 disabled 1 enabled 11 CH2DEN Channel 2 capture compare DMA reques...

Page 303: ...led Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH3IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 15 13 Reserved Must be kept at reset value 12 C...

Page 304: ...Reserved Must be kept at reset value 4 CH3IF Channel 3 s capture compare interrupt enable Refer to CH0IF description 3 CH2IF Channel 2 s capture compare interrupt enable Refer to CH0IF description 2 CH1IF Channel 1 s capture compare interrupt flag Refer to CH0IF description 1 CH0IF Channel 0 s capture compare interrupt flag This flag is set by hardware and cleared by software When channel 0 is in ...

Page 305: ...ration This bit is set by software in order to generate a capture or compare event in channel 0 it is automatically cleared by hardware When this bit is set the CH1IF flag is set the corresponding interrupt or DMA request is sent if enabled In addition if channel 1 is configured in input mode the current value of the counter is captured in TIMERx_CH0CV register and the CH0OF flag is set if the CH0...

Page 306: ...el 1 is configured as input IS1 is connected to CI0FE1 10 Channel 1 is configured as input IS1 is connected to CI1FE1 11 Channel 1 is configured as input IS1 is connected to ITS This mode is working only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register 7 CH0COMCEN Channel 0 output compare clear enable When this bit is set the O0CPRE signal is cleared when High le...

Page 307: ...able The PWM mode can be used without validating the shadow register only in single pulse mode SPM bit in TIMERx_CTL0 register is set This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 and CH0MS bit filed is 00 2 CH0COMFEN Channel 0 output compare fast enable When this bit is set the effect of an event on the trigger in input on the capture compare output will be acc...

Page 308: ...filter applied to CI0 0000 Filter disabled fSAMP fDTS N 1 0001 fSAMP fTIMER_CK N 2 0010 fSAMP fTIMER_CK N 4 0011 fSAMP fTIMER_CK N 8 0100 fSAMP fDTS 2 N 6 0101 fSAMP fDTS 2 N 8 0110 fSAMP fDTS 4 N 6 0111 fSAMP fDTS 4 N 8 1000 fSAMP fDTS 8 N 6 1001 fSAMP fDTS 8 N 8 1010 fSAMP fDTS 16 N 5 1011 fSAMP fDTS 16 N 6 1100 fSAMP fDTS 16 N 8 1101 fSAMP fDTS 32 N 5 1110 fSAMP fDTS 32 N 6 1111 fSAMP fDTS 32 N...

Page 309: ...t field specifies the direction of the channel and the input signal selection This bit field is writable only when the channel is not active CH3EN bit in TIMERx_CHCTL2 register is reset 00 Channel 3 is configured as output 01 Channel 3 is configured as input IS3 is connected to CI2FE3 10 Channel 3 is configured as input IS3 is connected to CI3FE3 11 Channel 3 is configured as input IS3 is connecte...

Page 310: ...ied when PROT 1 0 bit filed in TIMERx_CCHP register is 11 and CH2MS bit filed is 00 COMPARE MODE 3 CH2COMSEN Channel 2 compare output shadow enable When this bit is set the shadow register of TIMERx_CH2CV register which updates at each update event will be enabled 0 Channel 2 output compare shadow disable 1 Channel 2 output compare shadow enable The PWM mode can be used without validating the shad...

Page 311: ...ompare mode 7 4 CH2CAPFLT 3 0 Channel 2 input capture filter control An event counter is used in the digital filter in which a transition on the output occurs after N input events This bit field specifies the frequency used to sample CI2 input signal and the length of the digital filter applied to CI2 0000 Filter disable fSAMP fDTS N 1 0001 fSAMP fTIMER_CK N 2 0010 fSAMP fTIMER_CK N 4 0011 fSAMP f...

Page 312: ... value 13 CH3P Channel 3 capture compare function polarity Refer to CH0P description 12 CH3EN Channel 3 capture compare function enable Refer to CH0EN description 11 10 Reserved Must be kept at reset value 9 CH2P Channel 2 capture compare function polarity Refer to CH0P description 8 CH2EN Channel 2 capture compare function enable Refer to CH0EN description 7 6 Reserved Must be kept at reset value...

Page 313: ...l 0 disabled 1 Channel 0 enabled Counter register TIMERx_CNT Address offset 0x24 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw Bits Fields Descriptions 15 0 CNT 15 0 This bit filed indicates the current counter value Writing to this bit filed can change the value of the counter Prescaler register TIMERx_PSC Add...

Page 314: ..._CH0CV Address offset 0x34 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH0VAL 15 0 rw Bits Fields Descriptions 15 0 CH0VAL 15 0 Capture or compare value of channel0 When channel 0 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only...

Page 315: ... bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH2VAL 15 0 rw Bits Fields Descriptions 15 0 CH2VAL 15 0 Capture or compare value of channel 2 When channel 2 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 2 is configured in output mode this bit filed contains value to be compared to the counter ...

Page 316: ...A transfer count This filed is defined the number of DMA will access R W the register of TIMERx_DMATB 5 b0_0000 1 time transfer 5 b0_0001 2 times transfer 5 b1_0001 18 times transfer 7 5 Reserved Must be kept at reset value 4 0 DMATA 4 0 DMA transfer access start address This filed define the first address for the DMA access the TIMERx_DMATB When access is done through the TIMERx_DMA address first...

Page 317: ...Bits Fields Descriptions 15 0 DMATB 15 0 DMA transfer buffer When a read or write operation is assigned to this register the register located at the address range Start Addr Transfer Timer 4 will be accessed The transfer Timer is calculated by hardware and ranges from 0 to DMATC ...

Page 318: ...ongoing Single pulse mode is supported Auto reload function Interrupt output or DMA request on update event 15 3 3 Block diagram Figure 15 52 Basic timer block diagram provides details on the internal configuration of the basic timer Figure 15 52 Basic timer block diagram PSC Trigger processor Trigger Selector Counter Counter Register Interrupt Register set and update Interrupt collector APB BUS C...

Page 319: ...3 Normal mode internal clock divided by 1 CK_TIMER CEN PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event generate UPG 23 00 01 02 03 04 05 06 07 Update event UPE Prescaler The prescaler can divide the timer clock TIMER_CK to a counter clock PSC_CLK by any factor ranging from 1 to 65536 It is controlled by prescaler register TIMERx_PSC which can be changed ongoing but it is adopt...

Page 320: ...e counter restarts to count once again from 0 The update event is generated at each counter overflow When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If set the UPDIS bit in TIMERx_CTL0 register the update event is disabled When an update event occurs all the registers repetition counter auto reload re...

Page 321: ..._CLK PSC_CLK CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 05 06 07 Update event UPE Update interrupt flag UPIF CNT_REG 5F 60 Update event UPE Update interrupt flag UPIF Hardware set Software clear Hardware set TIMERx_PSC PSC 0 TIMERx_PSC PSC 1 TIMER_CK 08 63 62 61 00 01 02 03 CNT_CLK PSC_CLK ...

Page 322: ... Auto reload register 65 63 change CAR Vaule CNT_REG 5E 5F 60 61 62 63 64 65 00 01 02 62 63 00 Update event UPE Update interrupt flag UPIF Auto reload register 65 63 change CAR Vaule 65 63 Auto reload shadow register Hardware set Hardware set Software clear Hardware set ARSE 0 ARSE 1 Timer debug mode When the RISC V core halted and the TIMERx_HOLD configuration bit in DBG_CTL register set to 1 the...

Page 323: ...isable Counter continues after update event 1 Single pulse mode enable The CEN is cleared by hardware and the counter stops at next update event 2 UPS Update source This bit is used to select the update event sources by software 0 When enabled any of the following events generate an update interrupt or DMA request The UPG bit is set The counter generates an overflow or underflow event The slave mo...

Page 324: ...ter mode control These bits control the selection of TRGO signal which is sent in master mode to slave timers for synchronization function 000 Reset When the UPG bit in the TIMERx_SWEVG register is set or a reset is generated by the slave mode controller a TRGO pulse occurs And in the latter case the signal on TRGO is delayed compared to the actual reset 001 Enable This mode is useful to start sev...

Page 325: ...d 1 enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UPIF rc_w0 Bits Fields Descriptions 15 1 Reserved Must be kept at reset value 0 UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software 0 No update interrupt o...

Page 326: ...ssed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw Bits Fields Descriptions 15 0 CNT 15 0 This bit filed indicates the current counter value Writing to this bit filed can change the value of the counter Prescaler register TIMERx_PSC Address offset 0x28 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 ...

Page 327: ... or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15 0 rw Bits Fields Descriptions 15 0 CARL 15 0 Counter auto reload value This bit filed specifies the auto reload value of the counter Note When the timer is configured in input capture mode this register must be configured a non zero value such as 0xFFFF which is larger than user expected value ...

Page 328: ...cessor communication mode and hardware flow control protocol CTS RTS The data frame can be transferred from LSB or MSB bit The USART supports DMA function for high speed data communication except UART4 16 2 Characteristics NRZ standard format Asynchronous full duplex communication Half duplex single wire communication Programmable baud rate generator Divided from the peripheral clocks PCLK2 for US...

Page 329: ...t these events when the corresponding interrupt enable bits are set While USART0 1 2 is fully implemented UART3 4 is only partially implemented with the following features not supported Smartcard mode Synchronous mode Hardware flow control protocol CTS RTS 16 3 Function overview The interface is externally connected to another device by the main pins listed in Table 16 1 Description of USART impor...

Page 330: ... frame is configured by the WL bit in the USART_CTL0 register The last data bit can be used as parity check bit by setting the PCEN bit of in USART_CTL0 register When the WL bit is reset the parity bit is the 7th bit When the WL bit is set the parity bit is the 8th bit The method of calculating the parity bit is selected by the PM bit in USART_CTL0 register Figure 16 2 USART character frame 8 bits...

Page 331: ...rsampled by 16 the baud rate divider USARTDIV has the following relationship with the peripheral clock USARTDIV PCLK 16 Baud Rate 16 1 The peripheral clock is PCLK2 for USART0 and PCLK1 for USART1 2 and UART3 4 The peripheral clock must be enabled through the clock control unit before enabling the USART 1 Get USARTDIV by caculating the value of USART_BUAD If USART_BUAD 0x21D then INTDIV 33 0x21 FR...

Page 332: ... transmit procedure The software operating process is as follows 1 Write the WL bit in USART_CTL0 to set the data bits length 2 Set the STB 1 0 bits in USART_CTL1 to configure the number of stop bits 3 Enable DMA DENT bit in USART_CTL2 if multibuffer communication is selected 4 Set the baud rate in USART_BAUD 5 Set the TEN bit in USART_CTL0 6 Set the UEN bit in USART_CTL0 to enable the USART 7 Wai...

Page 333: ...ware directly or through DMA The REN bit should not be disabled when reception is ongoing or the current frame will be lost By default the receiver gets three samples to evaluate the value of a frame bit While in the oversampling 16 mode the 7th 8th and 9th samples are used If two or more samples of a frame bit is 0 the frame bit is confirmed as a 0 else 1 If the value of the three samples of any ...

Page 334: ... data buffer access To reduce the burden of the processor DMA can be used to access the transmitting and receiving data buffer The DENT bit in USART_CTL2 is used to enable the DMA transmission and the DENR bit in USART_CTL2 is used to enable the DMA reception When DMA is used for USART transmission DMA transfers data from internal SRAM to the transmit data buffer of the USART The configuration ste...

Page 335: ...uration steps when using DMA for USART reception Set the address of USART_DATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA interrupt enable priority etc Enable the DMA channel for USART When the number of the data received by USART reaches the DMA transfer n...

Page 336: ... a data frame can be transmitted If the TBE bit in USART_STAT is 0 and the nCTS signal is low the transmitter transmits the data frame When the nCTS signal goes high during a transmission the transmitter stops after the current transmission is accomplished Figure 16 8 Hardware flow control nCTS RX nRTS RTS flow control CTS flow control TX start data 2 start data 3 stop stop data 1 stop start data ...

Page 337: ...TL1 register the hardware sets the RWU bit and enters mute mode automatically In this situation the RBNE bit is not set If the address match method is selected the receiver does not check the parity value of an address frame by default If the PCEN bit in USART_CTL0 is set the MSB bit will be checked as the parity bit and the bit preceding the MSB bit is detected as the address bit 16 3 8 LIN mode ...

Page 338: ...ode The CK pin is the clock output of the synchronous USART transmitter and can be only activated when the TEN bit is enabled No clock pulse will be sent through the CK pin during the transmission of the start bit and stop bit The CLEN bit in USART_CTL1 can be used to determine whether the clock is output or not during the last address flag bit transmission The CPH bit in USART_CTL1 can be used to...

Page 339: ...t6 bit7 bit0 bit1 bit2 bit3 CK pin CPL 0 CPH 0 16 3 10 IrDA SIR ENDEC mode The IrDA mode is enabled by setting the IREN bit in USART_CTL2 The LMEN STB 1 0 CKEN bits in USART_CTL1 and HDEN SCEN bits in USART_CTL2 should be cleared in IrDA mode In IrDA mode the USART transmission data frame is modulated in the SIR transmit encoder and transmitted to the infrared LED through the TX pin The SIR receiv...

Page 340: ...SC clock While it can detect a pulse by chance if the pulse width is greater than 1 but smaller than 2 times of PSC clock Because the IrDA is a half duplex protocol the transmission and the reception should not be carried out at the same time in the IrDA SIR ENDEC block Figure 16 14 IrDA data modulation Normal tx frame Stop Start 1 0 0 0 0 0 0 1 1 1 1 Stop Start 1 0 1 1 1 1 0 0 0 0 0 TX pin Normal...

Page 341: ...PCLK The divide ratio is configured by the PSC 4 0 bits in USART_GP register The CK pin only provides a clock source to the smartcard The smartcard mode is a half duplex communication protocol When connected to a smartcard the TX pin must be configured as open drain and an external pull up resistor will be needed which drives a bidirectional line that is also driven by the smartcard The data frame...

Page 342: ...he data The NACK signal is enabled by setting the NKEN bit in USART_CTL2 The idle frame and break frame are not applied for the Smartcard mode 16 3 13 USART interrupts The USART interrupt events and flags are listed in Table 16 3 USART interrupt requests Table 16 3 USART interrupt requests Interrupt event Event flag Control register Enable Control bit Transmit data buffer empty TBE USART_CTL0 TBEI...

Page 343: ...03 User Manual 343 Figure 16 16 USART interrupt mapping diagram ORERR RBNEIE PERR PEIE LBDF LBDIE FERR NERR ORERR ERIE OR TCIE TBEIE CTSF CTSIE USART_INT TC TBE RBNE RBNEIE IDLEF IDLEIE RTF RTIE EBF EBIE DENR ...

Page 344: ...T_CTL2 is set this bit is set by hardware when the nCTS input toggles An interrupt occurs if the CTSIE bit in USART_CTL2 is set Software can clear this bit by writing 0 to it 0 The status of the nCTS line does not change 1 The status of the nCTS line has changed This bit is reserved for UART3 4 8 LBDF LIN break detected flag This bit is set when LIN break is detected An interrupt occurs if the LBD...

Page 345: ...occurs if the IDLEIE bit in USART_CTL0 is set Software can clear this bit by reading the USART_STAT and USART_DATA registers one by one 0 The USART module does not detect an IDLE frame 1 The USART module has detected an IDLE frame 3 ORERR Overrun error flag This bit is set if the RBNE is not cleared and a new data frame is received through the receive shift register An interrupt occurs if RBNEIE b...

Page 346: ...or 16 4 2 Data register USART_DATA Offset 0x04 Reset value Undefined This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DATA 8 0 rw Bits Fields Descriptions 31 9 Reserved Must be kept the reset value 8 0 DATA 8 0 Transmitted or received data value Software can write these bits to update the transmi...

Page 347: ...as to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UEN WL WM PCEN PM PERRIE TBEIE TCIE RBNEIE IDLEIE TEN REN RWU SBKCMD rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 14 Reserved Must be kept the reset value 13 UEN USART enable 0 USART disabled 1 USART enabled 12 WL Word length 0 8 data bit...

Page 348: ...R bit in USART_STAT is set 0 Read data register not empty interrupt and overrun error interrupt disabled 1 Read data register not empty interrupt and overrun error interrupt enabled 4 IDLEIE IDLE line detected interrupt enable If this bit is set an interrupt occurs when the IDLEF bit in USART_STAT is set 0 IDLE line detected interrupt disabled 1 IDLE line detected interrupt enabled 3 TEN Transmitt...

Page 349: ...ts Fields Descriptions 31 15 Reserved Must be kept the reset value 14 LMEN LIN mode enable 0 LIN mode disabled 1 LIN mode enabled This bit field cannot be written when the USART is enabled UEN 1 13 12 STB 1 0 Stop bits length 00 1 stop bit 01 0 5 stop bit 10 2 stop bits 11 1 5 stop bits This bit field cannot be written when the USART is enabled UEN 1 Only 1 stop bit and 2 stop bits are available f...

Page 350: ...bit is reserved for UART3 4 7 Reserved Must be kept the reset value 6 LBDIE LIN break detected interrupt enable If this bit is set an interrupt occurs when the LBDF bit in USART_STAT is set 0 LIN break detected interrupt is disabled 1 LIN break detected interrupt is enabled 5 LBLEN LIN break frame length This bit specifies the length of a LIN break frame 0 10 bits 1 11 bits This bit field cannot b...

Page 351: ...reserved for UART3 4 8 RTSEN RTS enable This bit enables the RTS hardware flow control function 0 RTS hardware flow control disabled 1 RTS hardware flow control enabled This bit field cannot be written when the USART is enabled UEN 1 This bit is reserved for UART3 4 7 DENT DMA request enable for transmission 0 DMA request is disabled for transmission 1 DMA request is enabled for transmission 6 DEN...

Page 352: ...DA mode enable This bit enables the IrDA mode of USART 0 IrDA disabled 1 IrDA enabled This bit field cannot be written when the USART is enabled UEN 1 This bit is reserved in USART1 0 ERRIE Error interrupt enable When DMA request for reception is enabled DENR 1 if this bit is set an interrupt occurs when any one of the FERR ORERR and NERR bits in USART_STAT is set 0 Error interrupt disabled 1 Erro...

Page 353: ... 00000000 Reserved never program this value 00000001 Divided by 1 00000010 Divided by 2 11111111 Divided by 255 When the USART works in IrDA normal mode these bits must be set to 00000001 When the USART smartcard mode is enabled the PSC 4 0 bits specify the division factor that is used to divide the peripheral clock APB1 APB2 to generate the smartcard clock CK The actual division factor is twice a...

Page 354: ...C interface provides DMA mode for users to reduce CPU overload 17 2 Characteristics Parallel bus to I2C bus protocol converter and interface Both master and slave functions with the same interface Bi directional data transfer between master and slave Supports 7 bit and 10 bit addressing and general call addressing Multi master capability Supports standard mode up to 100 kHz and fast mode up to 400...

Page 355: ... the device addressed by a master Multi master more than one master can attempt to control the bus at the same time without corrupting the message Synchronization procedure to synchronize the clock signal of two or more devices Arbitration procedure to ensure that if more than one master tries to control the bus simultaneously only one is allowed to do so and the winning master s message is not co...

Page 356: ...line is LOW see Figure 17 2 Data validation One clock pulse is generated for each data bit transferred Figure 17 2 Data validation SDA SCL 17 3 3 START and STOP condition All transactions begin with a START S and are terminated by a STOP P see Figure 17 3 START and STOP condition A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition A LOW to HIGH transition on the SD...

Page 357: ...dure A master may start a transfer only if the bus is free Two masters may generate a START condition within the minimum hold time of the START condition which results in a valid START condition on the bus Arbitration is then required to determine which master will complete its transmission Arbitration proceeds bit by bit During every bit while SCL is HIGH each master checks to see whether the SDA...

Page 358: ...ess byte2 W 0 ACK DATA0 ACK DATAN ACK Stop data transfer N 1 bytes From master to slave From slave to master Slave address byte1 hreader ACK 1 1 1 1 0 x x write Figure 17 8 I2C communication flow with 10 bit address Master Receive Start Slave address byte2 W 0 ACK DATA0 ACK DATAN NACK Stop data transfer N 1 bytes From master to slave From slave to master Slave address byte1 hreader ACK 1 1 1 1 0 x...

Page 359: ...he I2C bus The slave sets ADDSEND bit again after it detects the repeated START Sr condition and the following header Software needs to clear the ADDSEND bit again by reading I2C_STAT0 and then I2C_STAT1 3 Now I2C enters data transmission stage and hardware sets TBE bit because both the shift register and data register I2C_DATA are empty Once TBE is set Software should write the first byte of data...

Page 360: ...C_DATA Slave sends DATA N 1 Master sends Acknowledge Set TBE 7 Clear AERR I2C Line State Hardware Action Software Flow Master sends Header Slave sends Acknowledge Programming model in slave receiving mode As is shown in Figure 17 10 Programming model for slave receiving 10 bit address mode the following software procedure should be followed if users wish to make reception in slave receiver mode 1 ...

Page 361: ...ends Address Slave sends Acknowledge SCL stretched by slave Master sends DATA 1 Slave sends Acknowledge Data transmission Master sends DATA N Slave sends Acknowledge Master generates STOP condition Set ADDSEND 2 Clear ADDSEND Set RBNE Set STPDET 4 Read DATA x Set RBNE 3 Read DATA 1 5 Read DATA N 6 Clear STPDET I2C Line State Hardware Action Software Flow Set RBNE 1 Software initialization Programm...

Page 362: ...rdware sets TBE bit because both the shift register and data register I2C_DATA are empty Software now write the first byte data to I2C_DATA register but the TBE is not cleared because the write byte in I2C_DATA is moved to internal shift register immediately The I2C begins to transmit data to I2C bus as soon as shift register is not empty 6 During the first byte s transmission software can write t...

Page 363: ...ends Acknowledge Set TBE 9 Set STOP I2C Line State Hardware Action Software Flow 2 Set START Set SBSEND SCL stretched by master 3 Clear SBSEND SCL stretched by master SCL stretched by master Programming model in master receiving mode In master receiving mode a master is responsible for generating NACK for the last byte reception and then sending STOP condition on I2C bus So special attention shoul...

Page 364: ... bit again to generate a repeated START condition on I2C bus and SBSEND is set after the repeated START is sent out Software should clear the SBSEND bit by reading I2C_STAT0 and writing header to I2C_DATA Then the header is sent out to I2C bus and ADDSEND is set again Software should again clear ADDSEND by reading I2C_STAT0 and then I2C_STAT1 5 As soon as the first byte is received RBNE is set by ...

Page 365: ... SCL stretched by master 4 Set START Master generates repeated START condition Set SBSEND 4 Clear SBSEND SCL stretched by master Master sends Header Slave sends Acknowledge Set ADDSEND 4 Clear ADDSEND SCL stretched by master 6 Read DATA N 1 7 Clear ACKEN Set STOP Solution B 1 First of all software should enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make s...

Page 366: ...an read a byte from I2C_DATA until the master receives N 3 bytes As shown in Figure 17 13 Programming model for master receiving using solution B 10 bit address mode the N 2 byte is not read out by software so after the N 1 byte is received both BTC and RBNE are asserted The bus is stretched by master to prevent the reception of the last byte Then software should clear ACKEN bit 7 Software reads o...

Page 367: ... DATA N 2 I2C Line State Hardware Action Software Flow 2 Set START Set SBSEND SCL stretched by master 3 Clear SBSEND SCL stretched by master 4 Set START Master generates repeated START condition Set SBSEND 4 Clear SBSEND SCL stretched by master Master sends Header Slave sends Acknowledge Set ADDSEND 4 Clear ADDSEND SCL stretched by master 7 Clear ACKEN Slave sends DATA N 2 Master sends Acknowledge...

Page 368: ...igured number of byte has been transferred the DMA controller generates End of Transfer EOT interrupt When a master receives two or more bytes the DMALST bit in the I2C_CTL1 register should be set The I2C master will not send NACK after the last byte The software can set the STOP bit to generate a stop condition in the ISR of the DMA EOT interrupt When a master receives only one byte the ACKEN bit...

Page 369: ...ols there is a very useful distinction made between a System Host and all the other devices in the system that can have the names and functions of masters or slaves Time out feature SMBus has a time out feature which resets devices if a communication takes too long This explains the minimum clock frequency of 10 kHz to prevent locking up the bus I2C can be a DC bus meaning that a slave device stre...

Page 370: ...de SMBSEL 1 or DEFSMB flag in SMBus Device Mode and implement the function of ARP protocol 3 In order to support SMBus Alert Mode the software should response to SMBALT flag and implement the related function 17 3 12 Status errors and interrupts There are several status and error flags in I2C and interrupt may be asserted from these flags by setting some register bits refer to I2C register for det...

Page 371: ...alue 13 SALT SMBus Alert Issue alert through SMBA pin Software can set and clear this bit and hardware can clear this bit 0 Don t issue alert through SMBA pin 1 Issue alert through SMBA pin 12 PECTRANS PEC Transfer Software set and clear this bit while hardware clears this bit when PEC is transferred or START STOP condition detected or I2CEN 0 0 Don t transfer PEC value 1 Transfer PEC 11 POAP Posi...

Page 372: ...condition detected or I2CEN 0 0 START will not be sent 1 START will be sent 7 SS Whether to stretch SCL low when data is not ready in slave mode This bit is set and cleared by software 0 SCL Stretching is enabled 1 SCL Stretching is disabled 6 GCEN Whether or not to response to a General Call 0x00 0 Slave won t response to a General Call 1 Slave will response to a General Call 5 PECEN PEC Calculat...

Page 373: ... 1 if EVIE 1 9 EVIE Event interrupt enable 0 Event interrupt disabled 1 Event interrupt enabled means that interrupt will be generated when SBSEND ADDSEND ADD10SEND STPDET or BTC flag asserted or TBE 1 or RBNE 1 if BUFIE 1 8 ERRIE Error interrupt enable 0 Error interrupt disabled 1 Error interrupt enabled means that interrupt will be generated when BERR LOSTARB AERR OUERR PECERR SMBTO or SMBALT fl...

Page 374: ...e reset value 9 8 ADDRESS 9 8 Highest two bits of a 10 bit address 7 1 ADDRESS 7 1 7 bit address or bits 7 1 of a 10 bit address 0 ADDRESS0 Bit 0 of a 10 bit address 17 4 4 Slave address register 1 I2C_SADDR1 Address offset 0x0C Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ADDRESS2 7 1 DUADEN rw rw Bits Fields De...

Page 375: ...ERR LOSTAR B BERR TBE RBNE Reserved STPDET ADD10S END BTC ADDSEN D SBSEND rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 r r r r r r r Bits Fields Descriptions 15 SMBALT SMBus Alert status This bit is set by hardware and cleared by writing 0 0 SMBA pin not pulled down device mode or no Alert detected host mode 1 SMBA pin pulled down device mode or Alert detected host mode 14 SMBTO Timeout signal in SMB...

Page 376: ...ed START or STOP condition on I2C bus This bit is set by hardware and cleared by writing 0 0 No bus error 1 A bus error detected 7 TBE I2C_DATA is Empty during transmitting This bit is set by hardware after it moves a byte from I2C_DATA to shift register and cleared by writing a byte to I2C_DATA If both the shift register and I2C_DATA are empty writing I2C_DATA won t clear TBE refer to Programming...

Page 377: ... send the STOP condition or START condition Bit 0 I2CEN bit of the I2C_CTL0 is reset 0 BTC not asserted 1 BTC asserted 1 ADDSEND Address is sent in master mode or received and matches in slave mode This bit is set by hardware and cleared by reading I2C_STAT0 and reading I2C_STAT1 0 No address sent or received 1 Address sent out in master mode or a matched address is received in salve mode 0 SBSEND...

Page 378: ...ceived This bit is cleared by hardware after a STOP or a START condition or I2CEN 0 0 No general call address 00h received 1 General call address 00h received 3 Reserved Must be kept the reset value 2 TR Whether the I2C is a transmitter or a receiver This bit is cleared by hardware after a STOP or a START condition or I2CEN 0 or LOSTARB 1 0 Receiver 1 Transmitter 1 I2CBSY Busy flag This bit is cle...

Page 379: ...ndard speed mode Thigh Tlow CLKC TPCLK1 In fast speed mode if DTCY 0 Thigh CLKC TPCLK1 Tlow 2 CLKC TPCLK1 In fast speed mode if DTCY 1 Thigh 9 CLKC TPCLK1 Tlow 16 CLKC TPCLK1 17 4 9 Rise time register I2C_RT Address offset 0x20 Reset value 0x0002 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RISETIME 5 0 rw Bits Fields Descriptions ...

Page 380: ...ics 18 2 1 SPI characteristics Master or slave operation with full duplex or simplex mode Separate transmit and receive buffer 16 bits wide Data frame size can be 8 or 16 bits Bit order can be LSB or MSB Software and hardware NSS management Hardware CRC calculation transmission and checking Transmission and reception using DMA SPI TI mode supported SPI NSS pulse mode supported 18 2 2 I2S character...

Page 381: ... output Slave SPI clock input MISO I O Master Data reception line Slave Data transmission line Master with bidirectional mode Not used Slave with bidirectional mode Data transmission and reception line MOSI I O Master Data transmission line Slave Data reception line Master with bidirectional mode Data transmission and reception line Slave with bidirectional mode Not used NSS I O Software NSS mode ...

Page 382: ... and SPI will first send the LSB if LF 1 or the MSB if LF 0 The data order is fixed to MSB first in TI mode 18 5 2 NSS function Slave mode When slave mode is configured MSTMOD 0 SPI gets NSS level from NSS pin in hardware NSS mode SWNSSEN 0 or from SWNSS bit in software NSS mode SWNSSEN 1 and SPI transmits receives data only when NSS level is low In software NSS mode NSS pin is not used Master mod...

Page 383: ...eption with unidirectional connection MSTMOD 1 RO 1 BDEN 0 BDOEN Don t care MOSI Not used MISO Reception MTB Master transmission with bidirectional connection MSTMOD 1 RO 0 BDEN 1 BDOEN 1 MOSI Transmission MISO Not used MRB Master reception with bidirectional connection MSTMOD 1 RO 0 BDEN 1 BDOEN 0 MOSI Reception MISO Not used SFD Slave full duplex MSTMOD 0 RO 0 BDEN 0 BDOEN Don t care MOSI Recept...

Page 384: ...t used MISO Reception Figure 18 3 A typical full duplex connection Master MFD MISO MOSI SCK NSS Slave SFD MISO MOSI SCK NSS Figure 18 4 A typical simplex connection Master Receive Slave Transmit Master MRU MISO MOSI SCK NSS Slave STU MISO MOSI SCK NSS Figure 18 5 A typical simplex connection Master Transmit only Slave Receive Master MTU MISO MOSI SCK NSS Slave SRU MISO MOSI SCK NSS ...

Page 385: ...MOD RO BDEN and BDOEN depending on the operating modes described in SPI operating modes section 8 If Quad SPI mode is used set the QMOD bit in SPI_QCTL register Ignore this step if Quad SPI mode is not used 1 Enable the SPI set the SPIEN bit SPI basic transmission and reception sequence Transmission sequence After the initialization sequence the SPI is enabled and stays at idle state In master mod...

Page 386: ...escribed above The transmission mode MTU MTB STU or STB is similar to the transmission sequence of full duplex mode regardless of the RBNE and OVRE bits The master reception mode MRU or MRB is different from the reception sequence of full duplex mode In MRU or MRB mode after SPI is enabled the SPI continuously generates SCK until the SPI is disabled So the application should ignore the TBE flag an...

Page 387: ...es Figure 18 9 Timing diagram of TI slave mode SCK MOSI MISO NSS D7 D0 D0 D7 Td In slave TI mode after the last rising edge of SCK in transfer the slave begins to transmit the LSB bit of the last data byte and after a half bit time the master begins to sample the line To make sure that the master samples the right value the slave should continue to drive this bit after the falling sample edge of S...

Page 388: ...m depicts its timing diagram Figure 18 10 Timing diagram of NSS pulse with continuous transmission NSS SCK MISO MOSI MSB LSB LSB MSB MSB LSB MSB LSB Don t Care Don t Care Don t Care 1 SCK SPI disabling sequence Different sequences are used to disable the SPI in different operation modes MFD SFD Wait for the last RBNE flag and then receive the last data Confirm that TBE 1 and TRANS 0 At last disabl...

Page 389: ...omatically 18 5 5 CRC function There are two CRC calculators in SPI one for transmission and the other for reception The CRC calculation uses the polynomial defined in SPI_CRCPOLY register Application can enable the CRC function by setting CRCEN bit in SPI_CTL0 register The CRC calculators continuously calculate CRC for each bit transmitted and received on lines and the calculated CRC values can b...

Page 390: ...ced into slave mode The SPIEN and MSTMOD bits are write protected until the CONFERR is cleared The CONFERR bit of the slave cannot be set In a multi master configuration the device can be in slave mode with CONFERR bit set which means there might have been a multi master conflict for system control Rx overrun error RXORERR The RXORERR bit is set if a data is received when the RBNE is set That mean...

Page 391: ...ter All the user configuration registers are implemented in the control registers module including the TX buffer and RX buffer The clock generator is used to produce I2S communication clock in master mode The master control logic is implemented to generate the I2S_WS signal and control the communication in master mode The slave control logic is implemented to control the communication in slave mod...

Page 392: ...h is 24 bits or 32 bits two write or read operations to or from the SPI_DATA register are needed to complete the transmission of a frame In the case that the data length is 16 bits only one write or read operation to or from the SPI_DATA register is needed to complete the transmission of a frame When using 16 bit data packed in 32 bit frame 16 bit 0 is inserted by hardware automatically to extend ...

Page 393: ...be the higher 16 bits and the second one should be the lower 16 bits Figure 18 16 I2S Phillips standard timing diagram DTLEN 01 CHLEN 1 CKPL 0 I2S_CK I2S_SD 24 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 8 bit 0 MSB Figure 18 17 I2S Phillips standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 24 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 8 b...

Page 394: ... 0x0000 to extend the data to 32 bit format MSB justified standard For MSB justified standard I2S_WS and I2S_SD are updated on the falling edge of I2S_CK The SPI_DATA register is handled in the exactly same way as that for I2S Phillips standard The timing diagrams for each configuration are shown below Figure 18 20 MSB justified standard timing diagram DTLEN 00 CHLEN 0 CKPL 0 I2S_CK I2S_SD 16 bit ...

Page 395: ..._CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB Figure 18 27 MSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB LSB justified standard For LSB justified standard I2S_WS and I2S_SD are updated on the falling edge of I2S_CK In the case that the cha...

Page 396: ... is received the first data read from the SPI_DATA register is a 16 bit data The high 8 bits of this 16 bit data are zeros and the lower 8 bits are D 23 16 The second data read from the SPI_DATA register is D 15 0 Figure 18 30 LSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 16 bit 0 frame 1 channel left frame 2 channel right I2S_WS 16 bit data MSB LSB Figure 18 31 LSB j...

Page 397: ... synchronization mode timing diagram DTLEN 00 CHLEN 0 CKPL 1 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB LSB frame 1 frame 2 Figure 18 34 PCM standard short frame synchronization mode timing diagram DTLEN 10 CHLEN 1 CKPL 0 I2S_CK I2S_SD 32 bit data MSB I2S_WS MSB LSB frame 1 frame 2 Figure 18 35 PCM standard short frame synchronization mode timing diagram DTLEN 10 CHLEN 1 CKPL 1 I2S_CK I2S_SD 32 bit ...

Page 398: ...1 CKPL 1 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 16 bit 0 The timing diagrams for each configuration of the long frame synchronization mode are shown below Figure 18 40 PCM standard long frame synchronization mode timing diagram DTLEN 00 CHLEN 0 CKPL 0 I2S_CK I2S_SD 16 bits MSB I2S_WS MSB LSB frame 1 frame 2 13 bits Figure 18 41 PCM standard long frame synchronization mode timing ...

Page 399: ...CK I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 13 bits 8 bit 0 Figure 18 45 PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 13 bits 8 bit 0 Figure 18 46 PCM standard long frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 13 bits...

Page 400: ... the formulas shown in Table 18 4 I2S bitrate calculation formulas Table 18 4 I2S bitrate calculation formulas MCKOEN CHLEN Formula 0 0 I2SCLK DIV 2 OF 0 1 I2SCLK DIV 2 OF 1 0 I2SCLK 8 DIV 2 OF 1 1 I2SCLK 4 DIV 2 OF The relationship between audio sampling frequency Fs and I2S bitrate is defined by the following formula Fs I2S bitrate number of bits per channel number of channels So in order to get...

Page 401: ...nitialize I2S to slave mode only step 2 step 3 step 4 and step 5 should be done Step 1 Configure the DIV 7 0 bits the OF bit and the MCKOEN bit in the SPI_I2SPSC register to define the I2S bitrate and determine whether I2S_MCK needs to be provided or not Step 2 Configure the CKPL in the SPI_I2SCTL register to define the idle state clock polarity Step 3 Configure the I2SSEL bit the I2SSTD 1 0 bits ...

Page 402: ...equence As is mentioned before the RBNE flag indicates the receive buffer is not empty and an interrupt will be generated if the RBNEIE bit in the SPI_CTL1 register is set The reception sequence begins immediately when the I2SEN bit in the SPI_I2SCTL register is set At the beginning the receive buffer is empty RBNE is low When a reception sequence finishes the received data in the shift register i...

Page 403: ...erwise transmission underrun error occurs The TXURERR flag is set and an interrupt may be generated if the ERRIE bit in the SPI_CTL1 register is set In this case it is mandatory to disable and enable I2S to resume the communication In slave mode I2SCH is sensitive to the I2S_WS signal coming from the external master In order to disable I2S it is mandatory to clear the I2SEN bit after the TBE flag ...

Page 404: ...oftware This flag will not generate any interrupt I2S channel side flag I2SCH This flag indicates the channel side information of the current transfer and has no meaning in PCM mode It is updated when TBE rises in transmission mode or RBNE rises in reception mode This flag will not generate any interrupt 18 10 2 Error flags There are three error flags Transmission underrun error flag TXURERR This ...

Page 405: ... TBE Transmit buffer empty Write SPI_DATA register TBEIE RBNE Receive buffer not empty Read SPI_DATA register RBNEIE TXURERR Transmission underrun error Read SPI_STAT register ERRIE RXORERR Reception overrun error Read SPI_DATA register and then read SPI_STAT register FERR I2S format error Read SPI_STAT register ...

Page 406: ...scriptions 31 16 Reserved Must be kept at reset value 15 BDEN Bidirectional enable 0 2 line unidirectional transmit mode 1 1 line bidirectional transmit mode The information transfers between the MOSI pin in master and the MISO pin in slave 14 BDOEN Bidirectional transmit output enable When BDEN is set this bit determines the direction of transfer 0 Work in receive only mode 1 Work in transmit onl...

Page 407: ...bit This bit has no meaning in SPI TI mode 8 SWNSS NSS pin selection in NSS software mode 0 NSS pin is pulled low 1 NSS pin is pulled high This bit effects only when the SWNSSEN bit is set This bit has no meaning in SPI TI mode 7 LF LSB first mode 0 Transmit MSB first 1 Transmit LSB first This bit has no meaning in SPI TI mode 6 SPIEN SPI enable 0 SPI peripheral is disabled 1 SPI peripheral is ena...

Page 408: ... rw rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 TBEIE Transmit buffer empty interrupt enable 0 TBE interrupt is disabled 1 TBE interrupt is enabled An interrupt is generated when the TBE bit is set 6 RBNEIE Receive buffer not empty interrupt enable 0 RBNE interrupt is disabled 1 RBNE interrupt is enabled An interrupt is generated when the RBNE bit is set 5 ERRIE Errors ...

Page 409: ...e will be a DMA request on corresponding DMA channel 18 11 3 Status register SPI_STAT Address offset 0x08 Reset value 0x0002 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FERR TRANS RXORER R CONFER R CRCERR TXURER R I2SCH TBE RBNE rc_w0 r r r rc_w0 r r r r Bits Fields Descript...

Page 410: ...ual to the received CRC data at last This bit is set by hardware and cleared by writing 0 This bit is not used in I2S mode 3 TXURERR Transmission underrun error bit 0 No transmission underrun error occurs 1 Transmission underrun error occurs This bit is set by hardware and cleared by a read operation on the SPI_STAT register This bit is not used in SPI mode 2 I2SCH I2S channel side 0 The next data...

Page 411: ... transmission and reception transmit buffer and receive buffer are 8 bit If the data frame format is set to 16 bit data the SPI_DATA 15 0 is used for transmission and reception transmit buffer and receive buffer are 16 bit 18 11 5 CRC polynomial register SPI_CRCPOLY Address offset 0x10 Reset value 0x0007 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22...

Page 412: ...ceived bit when the TRANS is set a read to this register could return an intermediate value This register is reset when the CRCEN bit in SPI_CTL0 register or the SPIxRST bit in RCU reset register is set 18 11 7 TX CRC register SPI_TCRC Address offset 0x18 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 ...

Page 413: ... 11 10 9 8 7 6 5 4 3 2 1 0 Reserved I2SSEL I2SEN I2SOPMOD 1 0 PCMSMO D Reserved I2SSTD 1 0 CKPL DTLEN 1 0 CHLEN rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 I2SSEL I2S mode selection 0 SPI mode 1 I2S mode This bit should be configured when SPI I2S is disabled 10 I2SEN I2S enable 0 I2S is disabled 1 I2S is enabled This bit is not used in SPI mode 9 ...

Page 414: ...igured when I2S is disabled This bit is not used in SPI mode 2 1 DTLEN 1 0 Data length 00 16 bits 01 24 bits 10 32 bits 11 Reserved These bits should be configured when I2S mode is disabled These bits are not used in SPI mode 0 CHLEN Channel length 0 16 bits 1 32 bits The channel length must be equal to or greater than the data length This bit should be configured when I2S mode is disabled This bi...

Page 415: ...en I2S is disabled This bit is not used in SPI mode 8 OF Odd factor for the prescaler 0 Real divider value is DIV 2 1 Real divider value is DIV 2 1 This bit should be configured when I2S is disabled This bit is not used in SPI mode 7 0 DIV 7 0 Dividing factor for the prescaler Real divider value is DIV 2 OF DIV must not be 0 These bits should be configured when I2S is disabled These bits are not u...

Page 416: ...eter configuration as defined in the control registers 19 2 Characteristics Supported external memory SRAM PSRAM ROM NOR Flash Protocol translation between the AMBA and the multitude of external memory protocol Offering a variety of programmable timing parameters to meet user s specific needs Independent read write timing configuration to a sub set memory type 8 or 16 bits bus width Address and da...

Page 417: ...In the process of data transfer AHB access data width and memory data width may not be the same In order to ensure consistency of data transmission EXMC s read write accesses follow the following basic regulation When the width of AHB bus equals to the memory bus width No conversion is applied When the width of AHB bus is greater than memory bus width The AHB accesses are automatically split into ...

Page 418: ...0 address mapping Region0 0x60000000 NOR PSRAM HADDR 27 26 Address Regions Supported memory type 00 0x63FFFFFF HADDR 25 0 is the byte address whereas the external memory may not be byte accessed this will lead to address inconsistency EXMC can adjust HADDR to accommodate the data width of the external memory according to the following rules When data bus width of the external memory is 8 bits In t...

Page 419: ...nc Write enable EXMC_NWAIT Input Async Wait input signal EXMC_NL NADV Output Async Address valid Table 19 2 PSRAM muxed signal description EXMC Pin Direction Mode Functional description EXMC_A 25 16 Output Async Address Bus EXMC_D 15 0 Input output Async Data Bus EXMC_NE x Output Async Chip selection x 0 EXMC_NOE Output Async Read enable EXMC_NWE Output Async Write enable EXMC_NWAIT Input Async Wa...

Page 420: ...sses Async R 16 16 Async R 32 8 Split into 4 EXMC accesses Async R 32 16 Split into 2 EXMC accesses Async W 8 8 Async W 8 16 Use of byte lanes EXMC_NBL 1 0 Async W 16 8 Async W 16 16 Async W 32 8 Async W 32 16 NOR Flash PSRAM controller timing EXMC provides various programmable timing parameters and timing models for SRAM ROM PSRAM NOR Flash and other external static memory Table 19 4 NOR PSRAM co...

Page 421: ...ndependently according to EXMC_SNTCFGx register s configuration Asynchronous access timing diagram Mode AM NOR Flash address data bus multiplexing Figure 19 4 Multiplex mode read access 1 HCLK Address EXMC_A 25 16 Address Valid EXMC_NADV Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Data Mux EXMC_D 15 0 Memory Output Address Setup Time ASET 1 HCLK Data Setup Time DSET 1 HCLK Ad...

Page 422: ...sing edge to EXMC_NE 0 falling edge 15 8 DSET Depends on memory and user 7 4 AHLD Depends on memory and user 3 0 ASET Depends on memory and user Wait timing of asynchronous communication Wait feature is controlled by the bit ASYNCWAIT in register EXMC_SNCTLx During extern memory access data setup phase will be automatically extended by the active EXMC_NWAIT signal if ASYNCWAIT bit is set The exten...

Page 423: ...ata EXMC_D 15 0 Address Setup Time Data Setup Time Memory Output 4 HCLK Wait EXMC_NWAIT NRWTPOL 1 2 HCLK Data sampling point Figure 19 7 Write access timing diagram under async wait signal assertion Address EXMC_A 25 0 Wait EXMC_NWAIT NRWTPOL 0 Chip Enable EXMC_NEx Write Enable EXMC_NWE Data EXMC_D 15 0 Address Setup Time Data Setup Time 3 HCLK EXMC Output 1 HCLK Wait EXMC_NWAIT NRWTPOL 1 ...

Page 424: ...w Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 ASYNCWAIT Asynchronous wait 0 Disable the asynchronous wait feature 1 Enable the asynchronous wait feature 14 Reserved Must be kept at reset value 13 NRWTEN NWAIT signal enable For Flash memory access in burst mode this bit enables disables wait state insertion via the NWAIT signal 0 Disable NWAIT signal 1 Enable NWAIT signal...

Page 425: ...EN NOR region enable 0 Disable the corresponding memory bank 1 Enable the corresponding memory bank SRAM NOR Flash timing configuration registers EXMC_SNTCFGx x 0 Address offset 0x04 8 x x 0 Reset value 0x0FFF FFFF This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved BUSLAT 3 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSET 7 0 AHLD 3 0 ASET 3 0 r...

Page 426: ...etup time 256 HCLK period 7 4 AHLD 3 0 Address hold time This field is used to set the time of address hold phase 0x0 Reserved 0x1 Address hold time 2 HCLK 0xF Address hold time 16 HCLK 3 0 ASET 3 0 Address setup time This field is used to set the time of address setup phase Note meaningful only in asynchronous access of SRAM ROM NOR Flash 0x0 Address setup time 1 HCLK 0xF Address setup time 16 HC...

Page 427: ...which mailbox has to be transmitted first Three complete messages can be stored in each FIFO The FIFOs are managed completely by hardware Two receive FIFOs are used by hardware to store the incoming messages The CAN controller also provides all hardware functions for supporting the time triggered communication option for safety critical applications 20 2 Characteristics Supports CAN protocols vers...

Page 428: ...de Sleep working mode is the default mode after reset In sleep working mode the CAN is in the low power status while the CAN clock is stopped When SLPWMOD bit in CAN_CTL register is set the CAN enters the sleep working mode Then the SLPWS bit in CAN_STAT register is set To leave sleep working mode automatically the AWU bit in CAN_CTL register is set and the CAN bus activity is detected To leave sl...

Page 429: ... working mode to sleep working mode Set SLPWMOD bit in CAN_CTL register and wait the current transmission or reception completed Normal working mode to Initial working mode Set IWMOD bit in CAN_CTL register and wait the current transmission or reception completed 20 3 2 Communication modes The CAN interface has four communication modes Silent communication mode Loopback communication mode Loopback...

Page 430: ...D bit in CAN_BT register to enter loopback and silent communication mode or clear them to leave Loopback and silent communication mode is useful on self test The TX pin holds logical one The RX pin holds high impedance state Normal communication mode Normal communication mode is the default communication mode unless the LCMOD or SCMOD bit in CAN_BT register is set 20 3 3 Data transmission Transmis...

Page 431: ...smits finished Typically MTF is set when the frame in the transmit mailbox has been sent MTFNERR mailbox transmits finished and no error MTFNERR is set when the frame in the transmission mailbox has been sent without any error MAL mailbox arbitration lost MAL is set while the frame transmission is failed because of the arbitration lost MTE mailbox transmits error MTE is set while the frame transmi...

Page 432: ...rs are equal the lower mailbox number will be scheduled first 20 3 4 Data reception Reception register Two receive FIFOs are transparent to the application You can use receive FIFOs through five registers CAN_RFIFOx CAN_RFIFOMIx CAN_RFIFOMPx CAN_RFIFOMDATA0x and CAN_RFIFOMDATA1x FIFO s status and operation can be handled by CAN_RFIFOx register Reception frame data can be achieved through the regis...

Page 433: ...three frames It indicates FIFOx is overfull If the RFOD bit in CAN_CTL register is set the new frame is discarded If the RFOD bit in CAN_CTL register is reset the new frame is stored into the receive FIFO and the last frame in the receive FIFO is discarded Steps of receiving a message Step 1 Check the number of frames in the receive FIFO Step 2 Reading CAN_RFIFOMIx CAN_RFIFOMPx CAN_RFIFOMDATA0x an...

Page 434: ...TA1 31 21 FDATA1 20 3 FDATA1 2 0 SFID 10 0 EFID 17 0 FF FT 0 FDATA0 31 21 FDATA0 20 3 FDATA0 2 0 ID Mask Figure 20 8 16 bit mask mode filter FDATA0 15 5 FDATA0 4 0 SFID 10 0 FT FF EFID 17 15 FDATA1 15 5 FDATA1 4 0 SFID 10 0 FT FF EFID 17 15 FDATA0 31 21 FDATA0 20 16 FDATA1 31 21 FDATA1 20 16 ID Mask List mode The filter consists of frame identifiers The filter can decide whether a frame will be di...

Page 435: ...ank working and while filters not used by the application should be left deactivated Filtering index Each filter number corresponds to a filtering rule When the frame from the CAN bus passes the filters a filter number must associate with the frame The filter number is called filtering index It stores in the FI bits in CAN_RFIFOMPx when the frame is read by the application Each FIFO numbers the fi...

Page 436: ...TA1 32bit ID 16 Priority The filters have the priority 1 32 bit mode is higher than 16 bit mode 2 List mode is higher than mask mode 3 Smaller filter index value has the higher priority 20 3 6 Time triggered communication The time triggered CAN protocol is a higher layer protocol on top of the CAN data link layer Time triggered communication means that activities are triggered by the elapsing of t...

Page 437: ...ly read the messages continuous resynchronization is required Phase buffer segments are therefore inserted before and after the nominal sample point within a bit interval The CAN protocol regulates bus access by bit wise arbitration The signal propagation from sender to receiver and back to the sender must be completed within one bit time For synchronization purposes a further time segment the pro...

Page 438: ...oller itself does not send a recessive bit If a valid edge is detected in BS1 instead of SYNC_SEG BS1 is extended by up to SJW so that the sample point is delayed Conversely if a valid edge is detected in BS2 instead of SYNC_SEG BS2 is shortened by up to SJW so that the transmit point is moved earlier Baud rate The CAN s clock derives from the APB1 bus The CAN calculates its baud rate as follow 𝐵𝑎...

Page 439: ...nce specified in the CAN standard 128 occurrences of 11 consecutive recessive bits monitored on CAN RX If ABOR is set the CAN will start the recovering sequence automatically after it has entered Bus Off state If ABOR is cleared the software must initiate the recovering sequence by requesting CAN to enter and to leave initialization mode Note If the Bus off state cannot be recovery the bus off int...

Page 440: ...L1 bits in the CAN_RFIFO1 register are not 00 and RFNEIE1 in CAN_INTEN register is set Reception FIFO1 full RFF1 bit in the CAN_RFIFO1 register is set and RFFIE1 in CAN_INTEN register is set Reception FIFO1 overrun RFO1 bit in the CAN_RFIFO1 register is set and RFOIE1 in CAN_INTEN register is set Error and working mode change interrupt The error and working mode change interrupt can be generated b...

Page 441: ...t this bit define the CAN stop for debug or work normal If the CANx_HOLD in DBG_CTL register is clear this bit take not effect 0 CAN reception and transmission working normal even during debug 1 CAN reception and transmission stop working during debug 15 SWRST Software reset 0 No effect 1 Reset CAN with working mode of sleep This bit is automatically reset to 0 14 8 Reserved Must be kept at reset ...

Page 442: ...st in and first out 1 SLPWMOD Sleep working mode If this bit is set by software the CAN enter sleep working mode after current transmission or reception complete This bit can cleared by software or hardware If AWU bit in CAN_CTL register is set this bit is cleared by hardware when CAN bus activity detected 0 Disable sleep working mode 1 Enable sleep working mode 0 IWMOD Initial working mode 0 Disa...

Page 443: ...is bit is set by following event The BOERR bit in CAN_ERR register is set and BOIE bit in CAN_INTEN register is set Or the PERR bit in CAN_ERR register is set and PERRIE bit in CAN_INTEN register is set Or the WERR bit in CAN_ERR register is set and WERRIE bit in CAN_INTEN register is set Or the ERRN bits in CAN_ERR register are set to 1 to 6 not 0 and not 7 and ERRNIE in CAN_INTEN register is set...

Page 444: ... 27 26 25 24 23 22 21 20 19 18 17 16 TMLS2 TMLS1 TMLS0 TME2 TME1 TME0 NUM 1 0 MST2 Reserved MTE2 MAL2 MTFNER R2 MTF2 r r r r r r r rs rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MST1 Reserved MTE1 MAL1 MTFNER R1 MTF1 MST0 Reserved MTE0 MAL0 MTFNER R0 MTF0 rs rc_w1 rc_w1 rc_w1 rc_w1 rs rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 TMLS2 Transmit mailbox 2 last sending in tra...

Page 445: ...re when next transmit start 18 MAL2 Mailbox 2 arbitration lost This bit is set while the arbitration lost is occurred This bit reset by software when write 1 to this bit or MTF2 bit in CAN_TSTAT register This bit reset by hardware when next transmit start 17 MTFNERR2 Mailbox 2 transmit finished and no error This bit is set when the transmission finished and no error This bit reset by software when...

Page 446: ... 1 Mailbox 1 transmit finished 7 MST0 Mailbox 0 stop transmitting This bit is set by the software to stop mailbox 0 transmitting This bit is reset by the hardware while the mailbox 0 is empty 6 4 Reserved Must be kept at reset value 3 MTE0 Mailbox 0 transmit error This bit is set by hardware while the transmit error is occurred This bit reset by software when write 1 to this bit or MTF0 bit in CAN...

Page 447: ...e to start dequeuing a frame from receive FIFO0 This bit is reset by the hardware while the dequeuing is done 4 RFO0 Receive FIFO0 overfull This bit is set by hardware when receive FIFO0 is overfull and reset by software when write 1 to this bit 0 The receive FIFO0 is not overfull 1 The receive FIFO0 is overfull 3 RFF0 Receive FIFO0 full This bit is set by hardware when receive FIFO0 is full and r...

Page 448: ...n write 1 to this bit 0 The receive FIFO1 is not overfull 1 The receive FIFO1 is overfull 3 RFF1 Receive FIFO1 full This bit is set by hardware when receive FIFO1 is full and reset by software when write 1 to this bit 0 The receive FIFO1 is not full 1 The receive FIFO1 is full 2 Reserved Must be kept at reset value 1 0 RFL1 1 0 Receive FIFO1 length These bits are the length of the receive FIFO1 20...

Page 449: ...rrupt enable 9 PERRIE Passive error interrupt enable 0 Passive error interrupt disable 1 Passive error interrupt enable 8 WERRIE Warning error interrupt enable 0 Warning error interrupt disable 1 Warning error interrupt enable 7 Reserved Must be kept at reset value 6 RFOIE1 Receive FIFO1 overfull interrupt enable 0 Receive FIFO1 overfull interrupt disable 1 Receive FIFO1 overfull interrupt enable ...

Page 450: ...d 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RECNT 7 0 TECNT 7 0 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ERRN 2 0 Reserved BOERR PERR WERR rw r r r Bits Fields Descriptions 31 24 RECNT 7 0 Receive Error Count defined by the CAN standard 23 16 TECNT 7 0 Transmit Error Count defined by the CAN standard 15 7 Reserved Must be kept at reset value 6 4 ERRN 2 0 Error number These b...

Page 451: ...00 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SCMOD LCMOD Reserved SJW 1 0 Reserved BS2 2 0 BS1 3 0 rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BAUDPSC 9 0 rw Bits Fields Descriptions 31 SCMOD Silent communication mode 0 Silent communication disable 1 Silent communication enable 30 LCMOD Loopback communication mode 0 Loopback c...

Page 452: ...3 2 1 0 EFID 12 0 FF FT TEN rw rw rw rw Bits Fields Descriptions 31 21 SFID 10 0 EFID 28 1 8 The frame identifier SFID 10 0 Standard format frame identifier EFID 28 18 Extended format frame identifier 20 16 EFID 17 13 The frame identifier EFID 17 13 Extended format frame identifier 15 3 EFID 12 0 The frame identifier EFID 12 0 Extended format frame identifier 2 FF Frame format 0 Standard format fr...

Page 453: ...eserved Must be kept at reset value 8 TSEN Time stamp enable 0 Time stamp disable 1 Time stamp enable The TS 15 0 will be transmitted in the DB6 and DB7 in DL This bit is available while the TTC bit in CAN_CTL is set 7 4 Reserved Must be kept at reset value 3 0 DLENC 3 0 Data length code DLENC 3 0 is the number of bytes in a frame 20 4 11 Transmit mailbox data0 register CAN_TMDATA0x x 0 2 Address ...

Page 454: ... 21 20 19 18 17 16 DB7 7 0 DB6 7 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DB5 7 0 DB4 7 0 rw rw Bits Fields Descriptions 31 24 DB7 7 0 Data byte 7 23 16 DB6 7 0 Data byte 6 15 8 DB5 7 0 Data byte 5 7 0 DB4 7 0 Data byte 4 20 4 13 Receive FIFO mailbox identifier register CAN_RFIFOMIx x 0 1 Address offset 0x1B0 0x1C0 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 ...

Page 455: ...rame 1 Remote frame 0 Reserved Must be kept at reset value 20 4 14 Receive FIFO mailbox property register CAN_RFIFOMPx x 0 1 Address offset 0x1B4 0x1C4 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TS 15 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FI 7 0 Reserved DLENC 3 0 r r Bits Fields Descriptions 31 16 TS 15 0 Time stamp ...

Page 456: ...Descriptions 31 24 DB3 7 0 Data byte 3 23 16 DB2 7 0 Data byte 2 15 8 DB1 7 0 Data byte 1 7 0 DB0 7 0 Data byte 0 20 4 16 Receive FIFO mailbox data1 register CAN_RFIFOMDATA1x x 0 1 Address offset 0x1BC 0x1CC Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DB7 7 0 DB6 7 0 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DB5 7 0 DB4 7 ...

Page 457: ...et 0 not bank used to CAN0 When set 28 not bank used to CAN1 7 1 Reserved Must be kept at reset value 0 FLD Filter lock disable 0 Filter lock enable 1 Filter lock disable 20 4 18 Filter mode configuration register CAN_FMCFG Address offset 0x204 Reset value 0x0000 0000 This register has to be accessed by word 32 bit This register can be modified only when FLD bit in CAN_FCTL register is set 31 30 2...

Page 458: ... FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 28 Reserved Must be kept at reset value 27 0 FSx Filter scale 0 Filter x with 16 bit scale 1 Filter x with 32 bit scale 20 4 20 Filter associated FIFO register CAN_FAFIFO Address offset 0x214 Reset value 0x0000 0000 This register has to be accessed by word 32 bit This regi...

Page 459: ... FW10 FW9 FW8 FW7 FW6 FW5 FW4 FW3 FW2 FW1 FW0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 28 Reserved Must be kept at reset value 27 0 FWx Filter working 0 Filter x working disable 1 Filter x working enable 20 4 22 Filter x data y register CAN_FxDATAy x 0 27 y 0 1 Address offset 0x240 8 x 4 y x 0 27 y 0 1 Reset value 0xXXXX XXXX This register has to be accessed by w...

Page 460: ...GD32VF103 User Manual 460 Bits Fields Descriptions 31 0 FDx Filter data Mask mode 0 Mask match disable 1 Mask match enable List mode 0 List identifier bit is 0 1 List identifier bit is 1 ...

Page 461: ...ocol with HNP Host Negotiation Protocol and SRP Session Request Protocol Supports all the 4 types of transfer control bulk interrupt and isochronous Includes a USB transaction scheduler in host mode to handle USB transaction request efficiently Includes a 1 25KB FIFO RAM Supports 8 channels in host mode Includes 2 transmit FIFOs periodic and non periodic and a receive FIFO shared by all channels i...

Page 462: ...1 5 Function overview 21 5 1 USBFS clocks and working modes USBFS can operate as a host a device or a DRD Dual role Device it contains an internal full speed PHY The maximum speed supported by USBFS is full speed The internal PHY supports Full Speed and Low Speed in host mode supports Full speed in device mode and supports OTG mode with HNP and SRP The USB clock used by the USBFS should be 48MHz T...

Page 463: ...device mode FHM bit is cleared and FDM bit is set the VBUS detection circuit is connected to a GPIO pin USBFS continuously monitor the VBUS voltage by the GPIO pin and will immediately switch on the pull up resistor on DP line once that the VBUS voltage rise above the needed valid value This will cause a connection If the VBUS voltage falls below the needed valid value the pull up resistor on DP l...

Page 464: ...tate After PP bit is set by software the internal USB PHY is powered on and the USB port changes into disconnected state After a connection is detected USB port changes into connected state The USB port changes into enabled state after a port reset is performed on USB bus Figure 21 4 State transition diagram of host port Power off Dis connected Connected Enabled set PP bit clear PP bit or VBUS is ...

Page 465: ... and the USBFS wake up interrupt will be triggered if a host in suspend state detects a remote wakeup signal SOF generate USBFS sends SOF tokens on USB bus in host mode As described in USB 2 0 protocol SOF packets are generated by the host controller or hub transaction translator every 1ms in full speed links Each time after USBFS enters into enabled state it will send the SOF packet periodically ...

Page 466: ...quest queue If this is a channel disable request it immediately disables the channel and prepares to process the next entry If the current request is a transaction request and the USB bus time is enough for this transaction USBFS will employ SIE to generate this transaction on USB bus When the required bus time for the current request is not enough in the current frame and if this is a periodic re...

Page 467: ...e pull up resistor so that USB host will detect a disconnection on USB bus SOF tracking When USBFS receives a SOF packet on USB bus it will trigger a SOF interrupt and begin to count the bus time using local USB clock The frame number of the current frame is reported in FNRSOF filed in USBFS_DSTAT register When the USB bus time reaches EOF1 or EOF2 point End of Frame described in USB 2 0 protocol ...

Page 468: ...e set and the USBFS will begin to perform HNP protocol on bus and at last the result of HNP is reported in HNPS bit in USBFS_GOTGCS register Besides it is always available to get the current role host or device from COPM bit in USBFS_GINTF register SRP The Session Request Protocol SRP allows a B Device to request the A Device to turn on VBUS and start a session This protocol allows the A Device wh...

Page 469: ...pecial register area for the internal data FIFO reading and writing Figure 21 6 Host mode FIFO access register map describes the register memory area that the data FIFO can write This area can be read by any channel data FIFO The addresses in the figure are addressed in bytes Each channel has its own FIFO access register space although all Non periodic channels share the same FIFO and all the Peri...

Page 470: ...IFO0 Tx FIFO1 IEPTX0RSAR 15 0 IEPTX0FD IEPTX1FD IEPTX1RSAR 15 0 RXFD Start 0x00 End 0x13F Tx FIFO3 IEPTX3FD IEPTX3RSAR 15 0 USBFS provides a special register area for the internal data FIFO reading and writing Figure 21 8 Device mode FIFO access register map describes the register memory area where the data FIFO can write This area can be read by any endpoint FIFO The addresses in the figure are a...

Page 471: ...m USBFS_GCCFG register according to application s demand 4 Program USBFS_GRFLEN USBFS_HNPTFLEN_DIEP0TFLEN and USBFS_HPTFLEN register to configure the data FIFOs according to application s demand 5 Program USBFS_GINTEN register to enable Mode Fault and Host Port interrupt and set GINTEN bit in USBFS_GAHBCS register to enable global interrupt 6 Program USBFS_HPCS register and set PP bit 7 Wait for a...

Page 472: ...ble the channel Channel disable sequence Software can disable the channel by setting both CEN and CDIS bits at the same time USBFS will generate a channel disable request entry in request queue after the register setting operation When the request entry reaches the top of request queue it is processed by USBFS immediately For OUT channels the specified channel will be disabled immediately Then a C...

Page 473: ...esponding request queue and decreases the TLEN field in USBFS_HCHxLEN register by the written packet s size 4 When the request entry reaches the top of the request queue USBFS begins to process this request entry If bus time for the transaction indicated by the request entry is enough USBFS starts the OUT transaction on USB bus 5 When the OUT transaction indicated by the request entry finishes on ...

Page 474: ...FS_DOEPxCTL register with desired transfer type packet size etc 2 Program USBFS_DIEPINTEN or USBFS_DOEPINTEN register Set the desired interrupt enable bits 3 Program USBFS_DIEPxLEN or USBFS_DOEPxLEN register PCNT is the number of packets in a transfer and TLEN is the total bytes number of all the transmitted or received packets in a transfer For IN endpoint If PCNT 1 the single packet s size is eq...

Page 475: ...et or response with an NAK handshake based on the status of Rx FIFO and register configuration If the transaction finishes successfully USBFS receives and saves the data packet into Rx FIFO successfully and sends ACK handshake on USB bus PCNT in USBFS_DOEPxLEN register is decreased by 1 and the ACK flag is triggered otherwise the status flags report the transaction result 4 After all the data pack...

Page 476: ...pt flag Device mode ISOOPDIF Isochronous OUT packet dropped interrupt flag Device mode ENUMF Enumeration finished Device mode RST USB reset Device mode SP USB suspend Device mode ESP Early suspend Device mode GONAK Global OUT NAK effective Device mode GNPINAK Global IN Non Periodic NAK effective Device mode NPTXFEIF Non Periodic Tx FIFO empty interrupt flag Host Mode RXFNEIF Rx FIFO non empty inte...

Page 477: ...eset value 19 BSV B Session Valid described in OTG protocol 0 Vbus voltage level of a OTG B Device is below VBSESSVLD 1 Vbus voltage level of a OTG B Device is above VBSESSVLD Note Only accessible in OTG B Device mode 18 ASV A Session valid A host mode transceiver status 0 Vbus voltage level of a OTG A Device is below VASESSVLD 1 Vbus voltage level of a OTG A Device is above VASESSVLD The A Device...

Page 478: ...vice 0 HNP function is not enabled 1 HNP function is enabled Note Only accessible in host mode 9 HNPREQ HNP request This bit is set by software to start a HNP on the USB This bit can be cleared when HNPEND bit in USBFS_GOTGINTF register is set by writing zero to it or clearing the HNPEND bit in USBFS_GOTGINTF register 0 Don t send HNP request 1 Send HNP request Note Only accessible in device mode ...

Page 479: ...d rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved HNPEND SRPEND Reserved SESEND Reserved rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 DF Debounce finish Set by USBFS when the debounce during device connection is done Note Only accessible in host mode 18 ADTO A Device timeout Set by USBFS when the A Device s waiting for a B Device connect...

Page 480: ...GAHBCS Address offset 0x0008 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PTXFTH TXFTH Reserved GINTEN rw rw rw Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 PTXFTH Periodic Tx FIFO threshold 0 PTXFEIF will be triggered when the periodic transmit...

Page 481: ...register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FDM FHM Reserved rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UTT 3 0 HNPCEN SRPCEN Reserved TOC 2 0 rw r rw r rw rw Bits Fields Descriptions 31 Reserved Must be kept at reset value 30 FDM Force device mode Setting this bit will force the core to device mode irrespective of the USBFS ID inpu...

Page 482: ...ility enable Controls whether the SRP capability is enabled 0 SRP capability is disabled 1 SRP capability is enabled Note Accessible in both device and host modes 7 3 Reserved Must be kept at reset value 2 0 TOC 2 0 Timeout calibration USBFS always uses time out value required in USB 2 0 when waiting for a packet Application may use TOC 2 0 to add the value is in terms of PHY clock The frequency o...

Page 483: ... automatically clears this bit after the flush process completes After setting this bit application should wait until this bit is cleared before any other operation on USBFS Note Accessible in both device and host modes 4 RXFF Rx FIFO flush Application set this bit to flush data Rx FIFO Hardware automatically clears this bit after the flush process completes After setting this bit application shou...

Page 484: ...IF OEPIF IEPIF Reserved rc_w1 rc_w1 rc_w1 rc_w1 r r r rc_w1 rc_w1 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EOPFIF ISOOPDIF ENUMF RST SP ESP Reserved GONAK GNPINAK NPTXFEIF RXFNEIF SOF OTGIF MFIF COPM rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 r r r r rc_w1 r rc_w1 r Bits Fields Descriptions 31 WKUPIF Wakeup interrupt flag This interrupt is triggered when a resume signal in device mode or a remote wakeup...

Page 485: ... the flags that causing a port interrupt are cleared Note Only accessible in host mode 23 22 Reserved Must be kept at reset value 21 PXNCIF ISOONCIF Periodic transfer Not Complete Interrupt flag USBFS sets this bit when there are periodic transactions for current frame not completed at the end of frame Host mode Isochronous OUT transfer Not Complete Interrupt Flag At the end of a periodic frame de...

Page 486: ... isochronous OUT packet but cannot save it into Rx FIFO because the FIFO doesn t have enough space Note Only accessible in device mode 13 ENUMF Enumeration finished USBFS sets this bit after the speed enumeration finishes Read USBFS_DSTAT register to get the current device speed Note Only accessible in device mode 12 RST USB reset USBFS sets this bit when it detects a USB reset signal on bus Note ...

Page 487: ...by writing 1 Note Accessible in both host and device modes 2 OTGIF OTG interrupt flag USBFS sets this bit when the flags in USBFS_GOTGINTF register generate an interrupt Software should read USBFS_GOTGINTF register to get the source of this interrupt This bit is cleared after the flags in USBFS_GOTGINTF causing this interrupt are cleared Note Accessible in both host and device modes 1 MFIF Mode fa...

Page 488: ...odes 30 SESIE Session interrupt enable 0 Disable session interrupt 1 Enable session interrupt Note Accessible in both host and device modes 29 DISCIE Disconnect interrupt enable 0 Disable disconnect interrupt 1 Enable disconnect interrupt Note Only accessible in device mode 28 IDPSCIE ID pin status change interrupt enable 0 Disable connector ID pin status interrupt 1 Enable connector ID pin status...

Page 489: ...s IN transfer not complete interrupt Note Only accessible in device mode 19 OEPIE OUT endpoints interrupt enable 0 Disable OUT endpoints interrupt 1 Enable OUT endpoints interrupt Note Only accessible in device mode 18 IEPIE IN endpoints interrupt enable 0 Disable IN endpoints interrupt 1 Enable IN endpoints interrupt Note Only accessible in device mode 17 16 Reserved Must be kept at reset value 1...

Page 490: ... global non periodic IN NAK effective interrupt 1 Enable global non periodic IN NAK effective interrupt Note Only accessible in device mode 5 NPTXFEIE Non periodic Tx FIFO empty interrupt enable 0 Disable non periodic Tx FIFO empty interrupt 1 Enable non periodic Tx FIFO empty interrupt Note Only accessible in Host mode 4 RXFNEIE Receive FIFO non empty interrupt enable 0 Disable receive FIFO non e...

Page 491: ...ould only read this register after when Receive FIFO non empty interrupt flag bit of the global interrupt flag register RXFNEIF bit in USBFS_GINTF is triggered This register has to be accessed by word 32 bit Host mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RPCKST 3 0 DPID r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DPID BCOUNT 10 0 CNUM 3 0 r r r Bits Fields Descriptions 31 21 Rese...

Page 492: ...iptions 31 21 Reserved Must be kept at reset value 20 17 RPCKST 3 0 Received packet status 0001 Global OUT NAK generates an interrupt 0010 OUT data packet received 0011 OUT transfer completed generates an interrupt 0100 SETUP transaction completed generates an interrupt 0110 SETUP data packet received Others Reserved 16 15 DPID 1 0 Data PID The Data PID of the received OUT data packet 00 DATA0 10 ...

Page 493: ... Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 RXFD 15 0 Rx FIFO depth In terms of 32 bit words 1 RXFD 1024 Host non periodic transmit FIFO length register Device IN endpoint 0 transmit FIFO length USBFS_HNPTFLEN _DIEP0TFLEN Address offset 0x028 Reset value 0x0200 0200 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HNPTXFD IEP0...

Page 494: ...tart address The start address for endpoint0 transmit FIFO RAM is in term of 32 bit words Host non periodic transmit FIFO queue status register USBFS_HNPTFQSTAT Address offset 0x002C Reset value 0x0008 0200 This register reports the current status of the non periodic Tx FIFO and request queue The request queue holds IN OUT or other request entries in host mode Note In Device mode this register is ...

Page 495: ...t request queue 0 Request queue is Full 1 1 entry 2 2 entries n n entries 0 n 8 Others Reserved 15 0 NPTXFS 15 0 Non periodic Tx FIFO space The remaining space of the non periodic transmit FIFO In terms of 32 bit words 0 Non periodic Tx FIFO is full 1 1 word 2 2 words n n words 0 n NPTXFD Others Reserved Global core configuration register USBFS_GCCFG Address offset 0x0038 Reset value 0x0000 0000 T...

Page 496: ...e Comparer enable 0 VBUS B device comparer disabled 1 VBUS B device comparer enabled 18 VBUSACEN The VBUS A device Comparer enable 0 VBUS A device comparer disabled 1 VBUS A device comparer enabled 17 Reserved Must be kept at reset value 16 PWRON Power on This bit is the power switch for the internal embedded Full Speed PHY 0 Embedded Full Speed PHY power off 1 Embedded Full Speed PHY power on 15 ...

Page 497: ... 22 21 20 19 18 17 16 HPTXFD 15 0 r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HPTXFSAR 15 0 r rw Bits Fields Descriptions 31 16 HPTXFD 15 0 Host Periodic Tx FIFO depth In terms of 32 bit words 1 HPTXFD 1024 15 0 HPTXFSAR 15 0 Host periodic Tx FIFO RAM start address The start address for host periodic transmit FIFO RAM is in term of 32 bit words Device IN endpoint transmit FIFO length register USBFS...

Page 498: ...FIFO Tx RAM start address The start address for IN endpoint transmit FIFOx is in term of 32 bit words 21 7 2 Host control and status registers Host control register USBFS_HCTL Address offset 0x0400 Reset value 0x0000 0000 This register configures the core after power on in host mode Do not modify it after host initialization This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 2...

Page 499: ...9 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FRI 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 FRI 15 0 Frame interval This value describes the frame time in terms of PHY clocks Each time when port is enabled after a port reset operation USBFS use a proper value according to the current speed and software can write to this field to change the value T...

Page 500: ...turns to 0 after it reaches 0x3FFF Host periodic transmit FIFO queue status register USBFS_HPTFQSTAT Address offset 0x0410 Reset value 0x0008 0200 This register reports the current status of the host periodic Tx FIFO and request queue The request queue holds IN OUT or other request entries in host mode This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 501: ...ed 15 0 PTXFS 15 0 Periodic Tx FIFO space The remaining space of the periodic transmit FIFO In terms of 32 bit words 0 periodic Tx FIFO is full 1 1 word 2 2 words n n words 0 n PTXFD Others Reserved Host all channels interrupt register USBFS_HACHINT Address offset 0x0414 Reset value 0x0000 0000 When a channel interrupt is triggered USBFS set corresponding bit in this register and software should r...

Page 502: ... in USBFS_GINTF register This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CINTEN 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 CINTEN 7 0 Channel interrupt enable 0 Disable channel n interrupt 1 Enable channel n interrupt Each bit represents a channel Bit 0 for cha...

Page 503: ...ers Reserved 16 13 Reserved Must be kept at reset value 12 PP Port power This bit should be set before a port is used Because USBFS doesn t have power supply ability it only uses this bit to know whether the port is in powered state Software should ensure the true power supply on VBUS before setting this bit 0 Port is powered off 1 Port is powered on 11 10 PLST 1 0 Port line status Report the curr...

Page 504: ...4 Reserved Must be kept at reset value 3 PEDC Port enable disable change Set by the core when the status of the Port enable bit 2 in this register changes 2 PE Port Enable This bit is automatically set by USBFS after a USB reset signal finishes and cannot be set by software This bit is cleared by the following events A disconnect condition Software clearing this bit 0 Port disabled 1 Port enabled ...

Page 505: ...ftware should follow the operation guide to disable or enable a channel 29 ODDFRM Odd frame For periodic transfers interrupt or isochronous transfer this bit controls that whether in an odd frame or even frame this channel s transaction is desired to be processed 0 Even frame 1 Odd frame 28 22 DAR 6 0 Device address The address of the USB device that this channel wants to communicate with 21 20 Re...

Page 506: ...spective channel to know the source of the interrupt The flag bits in this register are all set by hardware and cleared by writing 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DTER REQOVR BBER USBER Reserved ACK NAK STALL Reserved CH TF rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 ...

Page 507: ...sponse to other requests during the request processing 0 TF Transfer finished All the transactions of this channel finish successfully and no error occurs For IN channel this flag will be triggered after PCNT bits in USBFS_HCHxLEN register reach zero For OUT channel this flag will be triggered when software reads and pops a TF status entry from the RxFIFO Host channel x interrupt enable register U...

Page 508: ...st queue overrun interrupt enable 0 Disable request queue overrun interrupt 1 Enable request queue overrun interrupt 8 BBERIE Babble error interrupt enable 0 Disable babble error interrupt 1 Enable babble error interrupt 7 USBERIE USB bus error interrupt enable 0 Disable USB bus error interrupt 1 Enable USB bus error interrupt 6 Reserved Must be kept at reset value 5 ACKIE ACK interrupt enable 0 D...

Page 509: ...N 18 16 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TLEN 15 0 rw Bits Fields Descriptions 31 Reserved Must be kept at reset value 30 29 DPID 1 0 Data PID Software should write this field before the transfer starts For OUT transfers this field controls the Data PID of the first transmitted packet For IN transfers this field controls the expected Data PID of the first received packet and DTERR wi...

Page 510: ...acket from the RxFIFO this field is decreased by the byte size of the packet 21 7 3 Device control and status registers Device configuration register USBFS_DCFG Address offset 0x0800 Reset value 0x0000 0000 This register configures the core in device mode after power on or after certain control commands or enumeration Do not change this register after device initialization This register has to be ...

Page 511: ... with a STALL handshake 0 Treat this packet as a normal packet and response according to the status of NAKS and STALL bits in USBFS_DOEPxCTL register 1 Send a STALL handshake and don t save the received OUT packet 1 0 DS 1 0 Device speed This field controls the device speed when the device connected to a host 11 Full speed Others Reserved Device control register USBFS_DCTL Address offset 0x0804 Re...

Page 512: ...bit again 6 4 Reserved Must be kept at reset value 3 GONS Global OUT NAK status 0 The handshake that USBFS response to OUT transaction packet and whether to save the OUT data packet are decided by Rx FIFO status endpoint s NAK and STALL bits 1 USHBS always responses to OUT transaction with NAK handshake and doesn t save the incoming OUT data packet 2 GINS Global IN NAK status 0 The response to IN ...

Page 513: ...token 7 3 Reserved Must be kept at reset value 2 1 ES 1 0 Enumerated speed This field reports the enumerated device speed Read this field after the ENUMF flag in USBFS_GINTF register is triggered 11 Full speed Others reserved 0 SPST Suspend status This bit reports whether device is in suspend state 0 Device is not in suspend state 1 Device is in suspend state Device IN endpoint common interrupt en...

Page 514: ...upt 5 Reserved Must be kept at reset value 4 EPTXFUDEN Endpoint Tx FIFO underrun interrupt enable bit 0 Disable endpoint Tx FIFO underrun interrupt 1 Enable endpoint Tx FIFO underrun interrupt 3 CITOEN Control In timeout interrupt enable bit 0 Disable control In timeout interrupt 1 Enable control In timeout interrupt 2 Reserved Must be kept at reset value 1 EPDISEN Endpoint disabled interrupt enab...

Page 515: ...kept at reset value 6 BTBSTPEN Back to back SETUP packets Only for control OUT endpoint interrupt enable bit 0 Disable back to back SETUP packets interrupt 1 Enable back to back SETUP packets interrupt 5 Reserved Must be kept at reset value 4 EPRXFOVREN Endpoint Rx FIFO overrun interrupt enable bit 0 Disable endpoint Rx FIFO overrun interrupt 1 Enable endpoint Rx FIFO overrun interrupt 3 STPFEN SE...

Page 516: ...pt at reset value 19 16 OEPITB 3 0 Device all OUT endpoint interrupt bits Each bit represents an OUT endpoint Bit 16 for OUT endpoint 0 bit 19 for OUT endpoint 3 15 4 Reserved Must be kept at reset value 3 0 IEPITB 3 0 Device all IN endpoint interrupt bits Each bit represents an IN endpoint Bit 0 for IN endpoint 0 bit 3 for IN endpoint 3 Device all endpoints interrupt enable register USBFS_DAEPINT...

Page 517: ...esents an OUT endpoint Bit 16 for OUT endpoint 0 bit 19 for OUT endpoint 3 15 4 Reserved Must be kept at reset value 3 0 IEPIE 3 0 IN endpoint interrupt enable bits 0 Disable IN endpoint n interrupt 1 Enable IN endpoint n interrupt Each bit represents an IN endpoint Bit 0 for IN endpoint 0 bit 3 for IN endpoint 3 Device VBUS discharge time register USBFS_DVBUSDT Address offset 0x0828 Reset value 0...

Page 518: ...USBFS_DVBUSPT Address offset 0x082C Reset value 0x0000 05B8 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DVBUSPT 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 DVBUSPT 11 0 Device VBUS pulsing time This field defines the pulsing time for VBUS The true pulsing...

Page 519: ...ts This field controls whether the TXFE bits in USBFS_DIEPxINTF registers are able to generate an endpoint interrupt bit in USBFS_DAEPINT register Bit 0 for IN endpoint 0 bit 3 for IN endpoint 3 0 Disable FIFO empty interrupt 1 Enable FIFO empty interrupt Device IN endpoint 0 control register USBFS_DIEP0CTL Address offset 0x0900 Reset value 0x0000 8000 This register has to be accessed by word 32 b...

Page 520: ...ndshake when receiving IN token USBFS will clear this bit after a SETUP token is received on the corresponding OUT endpoint 0 This bit has a higher priority than NAKS bit in this register and GINS bit in USBFS_DCTL register If both STALL and NAKS bits are set the STALL bit takes effect 20 Reserved Must be kept at reset value 19 18 EPTYPE 1 0 Endpoint type This field is fixed to 00 for control endp...

Page 521: ...Reserved EPTYPE 1 0 NAKS EOFRM DPID rs rs w w w w rw rw rs rw r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EPACT Reserved MPL 10 0 rw rw Bits Fields Descriptions 31 EPEN Endpoint enable Set by the application and cleared by USBFS 0 Endpoint disabled 1 Endpoint enabled Software should follow the operation guide to disable or enable an endpoint 30 EPD Endpoint disable Software can set this bit to disab...

Page 522: ...P token is received on the corresponding OUT endpoint Software is not able to clear it For interrupt or bulk IN endpoint Only software can clear this bit 20 Reserved Must be kept at reset value 19 18 EPTYPE 1 0 Endpoint type This field defines the transfer type of this endpoint 00 Control 01 Isochronous 10 Bulk 11 Interrupt 17 NAKS NAK status This bit controls the NAK status of USBFS when both STA...

Page 523: ...esn t make any response 14 11 Reserved Must be kept at reset value 10 0 MPL 10 0 This field defines the maximum packet length in bytes Device OUT endpoint 0 control register USBFS_DOEP0CTL Address offset 0x0B00 Reset value 0x0000 8000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EPEN EPD Reserved SNAK CNAK Reserved STALL SNOOP EPTYPE 1 0 NAKS Rese...

Page 524: ...eck the received data packet s CRC value 0 Snoop mode disabled 1 Snoop mode enabled 19 18 EPTYPE 1 0 Endpoint type This field is fixed to 00 for control endpoint 17 NAKS NAK status This bit controls the NAK status of USBFS when both STALL bit in this register and GONS bit in USBFS_DCTL register are cleared 0 USBFS sends data or handshake packets according to the status of the endpoint s Rx FIFO 1 ...

Page 525: ...et by the application and cleared by USBFS 0 Endpoint disabled 1 Endpoint enabled Software should follow the operation guide to disable or enable an endpoint 30 EPD Endpoint disable Software can set this bit to disable the endpoint Software should follow the operation guide to disable or enable an endpoint 29 SODDFRM SD1PID Set odd frame For isochronous OUT endpoints This bit has effect only if th...

Page 526: ...t check the received data packet s CRC value 0 Snoop mode disabled 1 Snoop mode enabled 19 18 EPTYPE 1 0 Endpoint type This field defines the transfer type of this endpoint 00 Control 01 Isochronous 10 Bulk 11 Interrupt 17 NAKS NAK status This bit controls the NAK status of USBFS when both STALL bit in this register and GONS bit in USBFS_DCTL register are cleared 0 USBFS sends handshake packets ac...

Page 527: ...e x endpoint_number Address offset 0x0908 endpoint_number 0x20 Reset value 0x0000 0080 This register contains the status and events of an IN endpoint when an IN endpoint interrupt occurs read this register for the respective endpoint to know the source of the interrupt The flag bits in this register are all set by hardware and cleared by writing 1 except the read only TXFE bit This register has to...

Page 528: ...ransfer finished This flag is triggered when all the IN transactions assigned to this endpoint have been finished Device OUT endpoint x interrupt flag register USBFS_DOEPxINTF x 0 3 where x endpoint_number Address offset 0x0B08 endpoint_number 0x20 Reset value 0x0000 0000 This register contains the status and events of an OUT endpoint when an OUT endpoint interrupt occurs read this register for th...

Page 529: ...triggered when a setup phase finished i e USBFS receives an IN or OUT token after a setup token 2 Reserved Must be kept at reset value 1 EPDIS Endpoint disabled This flag is triggered when an endpoint is disabled by the software s request 0 TF Transfer finished This flag is triggered when all the OUT transactions assigned to this endpoint have been finished Device IN endpoint 0 transfer length reg...

Page 530: ...ield is decreased by the byte size of the packet Device OUT endpoint 0 transfer length register USBFS_DOEP0LEN Address offset 0x0B10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved STPCNT 1 0 Reserved PCNT Reserved rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TLEN 6 0 rw Bits Fields Descriptions 31 Reserved Mu...

Page 531: ...int is enabled Each time software reads out a packet from the Rx FIFO this field is decreased by the byte size of the packet Device IN endpoint x transfer length register USBFS_DIEPxLEN x 1 3 where x endpoint_number Address offset 0x910 endpoint_number 0x20 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved MCPF 1 0 PCNT...

Page 532: ...fully writes a packet into the endpoint s Tx FIFO this field is decreased by the byte size of the packet Device OUT endpoint x transfer length register USBFS_DOEPxLEN x 1 3 where x endpoint_number Address offset 0x0B10 endpoint_number 0x20 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RXDPID STPCN T 1 0 PCNT 9 0 TLE...

Page 533: ...ly by USBFS after each successful data packet reception on bus 18 0 TLEN 18 0 Transfer length The total data bytes number of a transfer This field is the total data bytes of all the data packets desired to receive in an OUT transfer Program this field before the endpoint is enabled Each time after software reads out a packet from the RxFIFO this field is decreased by the byte size of the packet De...

Page 534: ...er USBFS_PWRCLKCTL Address offset 0x0E00 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SHCLK SUCLK rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 SHCLK Stop HCLK Stop the HCLK to save power 0 HCLK is not stopped 1 HCLK is stopped 0 SUCLK Stop...

Page 535: ...GD32VF103 User Manual 535 22 Revision history Table 22 1 Revision history Revision No Description Date 1 0 Initial Release Jun 5 2019 ...

Page 536: ...ry business industrial personal and or household applications only The Products are not designed intended or authorized for use as components in systems designed or intended for the operation of weapons weapons systems nuclear installations atomic energy control instruments combustion control instruments airplane or spaceship instruments transportation instruments traffic signal instruments life s...

Search results

Summary of Contents for GD32VF103

Reviews:

Related manuals for GD32VF103

Brands by name

Popular brands

GigaDevice Semiconductor GD32VF103, User Manual

Search results

Summary of Contents for GD32VF103

Reviews:

Related manuals for GD32VF103

Brands by name

Popular brands