Power
Supply
PlasmaQuant MS Series
194
control, they only indicate abnormal states on the outputs which cannot be corrected
by the controllers. If an error flag is asserted, most likely the instrument will need to be
stopped and cause of the error investigated.
Each voltage regulator is powered by a pair of voltage rails, so that its output can be
set to a selected DC value between the rails. The only exception is the detector focus
channel, which uses three rails, two to set the nominal output and the third for the
detector protection switch. All voltage rails are generated from the externally
su24 VDC, which is enabled by a relay controlled by the external interlock
signal. The input DC voltage is inverted to a number AC voltage by a DC/AC inverter.
Those AC voltages are either directly rectified or used to feed voltage multipliers to
produce even higher DC voltages (-580 V, -1.2 kV, +680 V, and -5.7 kV). There is a set
of filters used to reduce ripple and noise on the supply rails before they are connected
to the output regulators.
The detector focus power supply has dual role. The first (primary) is to provide bias
voltage to the detector focus electrode, and the second is to provide overload
protection for the detector. The output is switched to the protection mode whenever
the CPU board asserts the ‘detector protection’ signal. When it happens, the output
swings from its nominal value (-580 V), to a positive DC voltage of at least 160 V.
The interlock relay is shared with Ion Optics High Voltage Power Supply, that is, it gets
+24 VDC power via the IO HV PS. The CPU board also communicates with the detector
power supply via the shared serial interface. All messages sent to and from the
detector control circuits are relayed via this board. The CPU cannot be directly
connected to the detector interface—the two interfaces are similar, but not the same
(the detector interface is simplified version).
If the CPU interface cable is disconnected, all DACs outputs will be set to 0V, which will
also set most of the HV outputs to 0V. The exceptions are: EL, FR and DF channels,
which will settle at voltage different from 0V (V (El)
Η
+≈+11. 5V, V(FR)
Η
+≈+15V
(rail), and DF will go to the protection mode, so its voltage will 100V (up to
250 V)).
See 0220004900_Ionoptics for a detailed schematic and block diagram of the ion
optics and detector supply PCB.
It is a proprietary synchronous serial interface designed to send data for regulating
output voltages and to receive flags that indicate certain conditions of the output
stages. All signals of the interface are optically isolated from the CPU board, therefore
reducing the risk of damage propagation from faults that may happen at the HV
stages. In addition, this interface is used to send data for setting the HV regulators for
the detector biasing and to receive status flag from those regulators. Note that the
detector power supply and regulators are located on a separate board and that this
interface is used only for relaying the detector HV power supply messages.
Formats of data packets sent from the CPU board are different from those packets it
receives. A data packet sent from the CPU board to the voltage regulators contains the
following fields:
3 bits for selecting message destination (MSB clocked out first)
48 bits containing data for all 4 channels of the selected DAC (4 x 12bits, MSB sent
first for each channel)
Interface