Atmel XMEGA B, User Manual

Page: 271 / 415

271 XMEGA B [DATASHEET]
8291B–AVR–01/2013
21.7.1 Receiving Frames
The receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the
baud rate or XCK clock and shifted into the receive shift register until the first stop bit of a frame is received. A second
stop bit will be ignored by the receiver. When the first stop bit is received and a complete serial frame is present in the
receive shift register, the contents of the shift register will be moved into the receive buffer. The receive complete
interrupt flag (RXCIF) is set, and the optional interrupt is generated.
The receiver buffer can be read by reading the data register (DATA) location. DATA should not be read unless the
receive complete interrupt flag is set. When using frames with fewer than eight bits, the unused most-significant bits are
read as zero. If 9-bit characters are used, the ninth bit must be read from the RXB8 bit before the low byte of the
character is read from DATA.
21.7.2 Receiver Error Flags
The USART receiver has three error flags. The frame error (FERR), buffer overflow (BUFOVF) and parity error (PERR)
flags are accessible from the status register. The error flags are located in the receive FIFO buffer together with their
corresponding frame. Due to the buffering of the error flags, the status register must be read before the receive buffer
(DATA), since reading the DATA location changes the FIFO buffer.
21.7.3 Parity Checker
When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with
the parity bit of the corresponding frame. If a parity error is detected, the parity error flag is set.
21.7.4 Disabling the Receiver
A disabling of the receiver will be immediate. The receiver buffer will be flushed, and data from ongoing receptions will be
lost.
21.7.5 Flushing the Receive Buffer
If the receive buffer has to be flushed during normal operation, read the DATA location until the receive complete
interrupt flag is cleared.
21.8 Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock
recovery unit is used for synchronizing the incoming asynchronous serial frames at the RxD pin to the internally
generated baud rate clock. It samples and low-pass filters each incoming bit, thereby improving the noise immunity of the
receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the
rate of the incoming frames, and the frame size in number of bits.
21.8.1 Asynchronous Clock Recovery
The clock recovery unit synchronizes the internal clock to the incoming serial frames. Figure 21-6 on page 272 illustrates
the sampling process for the start bit of an incoming frame. The sample rate is 16 times the baud rate for normal mode,
and eight times the baud rate for double speed mode. The horizontal arrows illustrate the synchronization variation due
to the sampling process. Note the larger time variation when using the double speed mode of operation. Samples
denoted as zero are samples done when the RxD line is idle; i.e., when there is no communication activity.