Atmel XMEGA B, User Manual

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83 XMEGA B [DATASHEET]
8291B–AVR–01/2013
Figure 7-6. DFLL reference clock selection.
The ideal counter value representing the frequency ratio between the internal oscillator and a 1.024kHz reference clock
is loaded into the DFLL oscillator compare register (COMP) during reset. For the 32MHz oscillator, this register can be
written from software to make the oscillator run at a different frequency or when the ratio between the reference clock
and the oscillator is different (for example when the USB start of frame is used). The 48MHz calibration values must be
read from the production signature row and written to the 32MHz CAL register before the DFLL is enabled with USB SOF
as reference source.
The value that should be written to the COMP register is given by the following formula:
When the DFLL is enabled, it controls the ratio between the reference clock frequency and the oscillator frequency. If the
internal oscillator runs too fast or too slow, the DFLL will decrement or increment its calibration register value by one to
adjust the oscillator frequency. The oscillator is considered running too fast or too slow when the error is more than a half
calibration step size.
32.768 kHz Crystal Osc
External Clock
32.768 kHz Int. Osc
DFLL32M
32 MHz Int. RCOSC
DFLL2M
2 MHz Int. RCOSC
clk
RC32MCREF
clk
RC2MCREF
TOSC1
TOSC2
XTAL1
PC[7:0]
DIV32 DIV32
XOSCSEL
USB Start of Frame