Atmel XMEGA B, User Manual

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361 XMEGA B [DATASHEET]
8291B–AVR–01/2013
As shown in the state diagram, the run test/idle state need not be entered between selecting JTAG instructions and using
data registers.
Note: Independently of the initial state of the TAP controller, the test logic reset state can always be entered by holding
TMS high for five TCK clock periods.
28.4 JTAG Instructions
The instruction register is four bits wide. Listed below are the JTAG instructions for boundary scan operation and the
PDICOM instruction used for accessing the PDI in JTAG mode.
The lsb is shifted in and out first for all shift registers.
The opcode for each instruction is shown beside the instruction name in hex format. The text describes which data
register is selected as the path between TDI and TDO for each instruction.
28.4.1 EXTEST; 0x1
EXTEST is the instruction for selecting the boundary scan chain as the data register for testing circuitry external to the
AVR XMEGA device package. The instruction is used for sampling external pins and loading output pins with data. For
the I/O port pins, both output control (DIR) and output data (OUT) are controllable via the scan chain, while the output
control and actual pin value are observable. The contents of the latched outputs of the boundary scan chain are driven
out as soon as the JTAG instruction register is loaded with the EXTEST instruction.
The active states are:

Capture DR: Data on the external pins are sampled into the boundary scan chain

Shift DR: Data in the Boundary-scan Chain are shifted by the TCK input

Update DR: Data from the scan chain are applied to output pins
28.4.2 IDCODE; 0x3
IDCODE is the instruction for selecting the 32-bit ID register as the data register. The ID register consists of a version
number, a device number, and the manufacturer code chosen by the Joint Electron Devices Engineering Council
(JEDEC). This is the default instruction after power up.
The active states are:

Capture DR: Data in the IDCODE register are sampled into the device identification register

Shift DR: The IDCODE scan chain is shifted by the TCK input
28.4.3 SAMPLE/PRELOAD; 0x2
SAMPLE/PRELOAD is the instruction for preloading the output latches and taking a snapshot of the input/output pins
without affecting system operation. However, the output latches are not connected to the pins. The boundary scan chain
is selected as the data register. Since each of the SAMPLE and PRELOAD instructions implements the functionality of
the other, they share a common binary value, and can be treated as a single, merged instruction.
The active states are:

Capture DR: Data on the external pins are sampled into the boundary scan chain

Shift DR: The boundary scan chain is shifted by the TCK input

Update DR: Data from the boundary scan chain are applied to the output latches, but the output latches are not
connected to the pins
28.4.4 BYPASS; 0xf
BYPASS is the instruction for selecting the bypass register for the data register. This instruction can be issued to make
the shortest possible scan chain through the device.