Atmel XMEGA B, User Manual

Page: 281 / 415

281 XMEGA B [DATASHEET]
8291B–AVR–01/2013
21.15.4 CTRLB – Control register B

Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 4 – RXEN: Receiver Enable
Setting this bit enables the USART receiver. The receiver will override normal port operation for the RxD pin, when
enabled. Disabling the receiver will flush the receive buffer, invalidating the FERR, BUFOVF, and PERR flags.

Bit 3 – TXEN: Transmitter Enable
Setting this bit enables the USART transmitter. The transmitter will override normal port operation for the TxD pin, when
enabled. Disabling the transmitter (writing TXEN to zero) will not become effective until ongoing and pending
transmissions are completed; i.e., when the transmit shift register and transmit buffer register do not contain data to be
transmitted. When disabled, the transmitter will no longer override the TxD port.
 Bit 2 – CLK2X: Double Transmission Speed
Setting this bit will reduce the divisor of the baud rate divider from16 to 8, effectively doubling the transfer rate for
asynchronous communication modes. For synchronous operation, this bit has no effect and should always be written to
zero. This bit must be zero when the USART communication mode is configured to IRCOM.
This bit is unused in master SPI mode operation.

Bit 1 – MPCM: Multiprocessor Communication Mode
This bit enables the multiprocessor communication mode. When the MPCM bit is written to one, the USART receiver
ignores all the incoming frames that do not contain address information. The transmitter is unaffected by the MPCM
setting. For more detailed information, see
“Multiprocessor Communication Mode” on page 277 .
This bit is unused in master SPI mode operation.

Bit 0 – TXB8: Transmit Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. When
used, this bit must be written before writing the low bits to DATA.
This bit is unused in master SPI mode operation.
21.15.5 CTRLC – Control register C
Note: 1. Master SPI mode.

Bits 7:6 – CMODE[1:0]: Communication Mode
These bits select the mode of operation of the USART as shown in Table 21-7 .
Bit 7 6 5 4 3 2 1 0
+0x04
– – – RXEN TXEN CLK2X MPCM TXB8
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x05
CMODE[1:0] PMODE[1:0] SBMODE CHSIZE[2:0]
+0x05
(1)
CMODE[1:0] – – – UDORD UCPHA –
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 1 1 0