Atmel XMEGA B, User Manual

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371 XMEGA B [DATASHEET]
8291B–AVR–01/2013
29.4 PDI Controller
The PDI controller performs data transmission/reception on a byte level, command decoding, high-level direction control,
control and status register access, exception handling, and clock switching (PDI_CLK or TCK). The interaction between
an external programmer and the PDI controller is based on a scheme where the programmer transmits various types of
requests to the PDI controller, which in turn responds according to the specific request. A programmer request comes in
the form of an instruction, which may be followed by one or more byte operands. The PDI controller response may be
silent (e.g., a data byte is stored to a location within the device), or it may involve data being returned to the programmer
(e.g., a data byte is read from a location within the device).
29.4.1 Accessing Internal Interfaces
After an external programmer has established communication with the PDI, the internal interfaces are not accessible, by
default. To get access to the NVM controller and the nonvolatile memories for programming, a unique key must be
signaled by using the KEY instruction. The internal interfaces are accessed as one linear address space using a
dedicated bus (PDIBUS) between the PDI and the internal interfaces. The PDIBUS address space is shown in
Figure 33-
3 on page 436 . The NVM controller must be enabled for the PDI controller to have any access to the NVM interface. The
PDI controller can access the NVM and NVM controller in programming mode only. The PDI controller does not need to
access the NVM controller's data or address registers when reading or writing NVM.
29.4.2 NVM Programming Key
The key that must be sent using the KEY instruction is 64 bits long. The key that will enable NVM programming is:
0x1289AB45CDD888FF
29.4.3 Exception Handling
There are several situations that are considered exceptions from normal operation. The exceptions depend on whether
the PDI is in RX or TX mode.
While the PDI is in RX mode, the exceptions are:

PDI:

The physical layer detects a parity error

The physical layer detects a frame error

The physical layer recognizes a BREAK character (also detected as a frame error)
While the PDI is in TX mode, the exceptions are:

PDI:

The physical layer detects a data collision
Exceptions are signaled to the PDI controller. All ongoing operations are then aborted, and the PDI is put in ERROR
state. The PDI will remain in ERROR state until a BREAK is sent from the external programmer, and this will bring the
PDI back to its default RX state.
Due to this mechanism, the programmer can always synchronize the protocol by transmitting two successive BREAK
characters.
29.4.4 Reset Signalling
Through the reset register, the programmer can issue a reset and force the device into reset. After clearing the reset
register, reset is released, unless some other reset source is active.
29.4.5 Instruction Set
The PDI has a small instruction set used for accessing both the PDI itself and the internal interfaces. All instructions are
byte instructions. The instructions allow an external programmer to access the PDI controller, the NVM controller and the
nonvolatile memories.