Atmel XMEGA B, User Manual

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183 XMEGA B [DATASHEET]
8291B–AVR–01/2013
14.10.5 INTCTRLA – Interrupt Enable register A

Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.

Bit 3:2 – HUNFINTLVL[1:0]: High-byte Timer Underflow Interrupt Level
These bits enable the high-byte timer underflow interrupt and select the interrupt level, as described in “Interrupts and
Programmable Multilevel Interrupt Controller” on page 118 . The enabled interrupt will be triggered when HUNFIF in the
INTFLAGS register is set.

Bit 1:0 – LUNFINTLVL[1:0]: Low-byte Timer Underflow Interrupt Level
These bits enable the low-byte timer underflow interrupt and select the interrupt level, as described in “Interrupts and
Programmable Multilevel Interrupt Controller” on page 118 . The enabled interrupt will be triggered when LUNFIF in the
INTFLAGS register is set.
14.10.6 INTCTRLB – Interrupt Enable register B
 Bit 7:0 – LCMPxINTLVL[1:0]: Low-byte Compare x Interrupt Level
These bits enable the low-byte timer compare interrupt and select the interrupt level, as described in “Interrupts and
Programmable Multilevel Interrupt Controller” on page 118 . The enabled interrupt will be triggered when LCMPxIF in the
INTFLAGS register is set.
14.10.7 CTRLF – Control register F

Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.

Bit 3:2 – CMD[1:0]: Timer/Counter Command
These command bits are used for software control of timer/counter update, restart, and reset. The command bits are
always read as zero. The CMD bits must be used together with CMDEN.
Bit 7 6 5 4 3 2 1 0
+0x06
– – – – HUNFINTLVL[1:0] LUNFINTLVL[1:0]
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x07
LCMPDINTLVL[1:0] LCMPCINTLVL[1:0] LCMPBINTLVL[1:0] LCMPAINTLVL[1:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x08
– – – – CMD[1:0] CMDEN[1:0]
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0